IEEE P1800 SV-BC Technical Committee
SystemVerilog Basic Committee
The SV-BC is the subcommittee of the IEEE P1800
SystemVerilog Technical Committee tasked with
maintaining and extending the design features of the System Verilog language as well as addressing issues from the Verilog language defined in the 1364 standards.
Links
mailto:sv-bc@eda.org
SV-BC Operating Guidelines
SV-BC Email Reflector Archives
1800-2009 Ballot Resolution
1800-2008
SV-BC Issues
To subscribe to the SV-BC email reflectors,
please send an email to
majordomo@eda.org
with the following in the body of the email:
subscribe sv-bc <email address>