Aa!߀Vff ePM pp0 ` P0`  0@`0@ $H $ d HHUÙ̀̀ff@  d Footnote TableFootnote**/ - :;,.!? synophp5-q g 0g?LOPH2,1.1H3,1.1.1 H4,1.1.1.1 H5,1.1.1.1.1TOCH2,1.1H3,1.1.1 H4,1.1.1.1 H5,1.1.1.1.1 NumberedList1 NumberedList27APIsDirectCMyTypePLIs SystemVerilogVerilogarravaluebvaluecalleeconst d=destination d=dimension endfunctionextern foo(inputhinhouti=bit i=startinginoutintlongintmallocmy_tabmy_valueptrs=scalars=sourceshortint shortrealstructsubrangesvsvBitsvBitPackedArrRefsvGetBitArrElemsvGetLogicArrElemsvHandlesvLogicsvLogicPackedArrRefsvPutBitArrElemsvPutLogicArrElemsvScalarsvSizeOfBitPackedArrsvSizeOfLogicPackedArrsv_CANONICAL_SIZEsv_CANONICAL_SIZE(WIDTH sv_handlesv_xsv_ztypedef typedefedunsizedw=widthAHADALAEATAZAF   EquationVariablesCn  "=Yfҋe$&')*,?A C D F G I Ӵ U   W X ֣֥ЫЭЯбвдезLNOPRSKM`[?@L $. NVPR  #!)V !c"&& &$$z%|%'&c'e'e"#)q(s(**++,,֦֭֫8 R31627: H3,1.1.1: 1.4.6 Mapping between System Verilog ranges and normalized ranges; B49431: H4,1.1.1.1: 1.6.1.3 Implementation dependent representation@ "15864: H3,1.1.1: 1.4.4 Basic Types/ 091204: TableTitle: Table11: Mapping data types2 >35301: TableTitle: Table12: Encoding of bits in svLogicVec325 &36814: H4,1.1.1.1: 1.7.3.1 Bit selectsM '95760: H4,1.1.1.1: 1.7.3.2 Part selectsP >32292: H3,1.1.1: 1.6.1 Binary compatibility include file svc.hA )98070: H3,1.1.1: 1.4.1 svc.h include fileV &84427: H3,1.1.1: 1.5.6 Input argumentsZ 44331: H2,1.1: 1.8 Include files /52619: x.Annex.Heading: Annex A DirectC C-layer [88142: x.Annex.H2,A.1.1: A.7.5 Allocating actual arguments for SystemVerilog-specific types% Z44514: x.Annex.H2,A.1.1: A.10.11 Example 6 binary compatible calls of exported functions        #)*+ , >fo#R31627: H3,1.1.1: 1.4.6 Mapping between System Verilog ranges and normalized ranges>fo#B49431: H4,1.1.1.1: 1.6.1.3 Implementation dependent representation>fo#R31627: H3,1.1.1: 1.4.6 Mapping between System Verilog ranges and normalized ranges>fo#"15864: H3,1.1.1: 1.4.4 Basic Types>foh091204: TableTitle: Table11: Mapping data types>fo!>35301: TableTitle: Table12: Encoding of bits in svLogicVec32>fo#&36814: H4,1.1.1.1: 1.7.3.1 Bit selects>fo<#'95760: H4,1.1.1.1: 1.7.3.2 Part selects>fo #>32292: H3,1.1.1: 1.6.1 Binary compatibility include file svc.h>fo!#>32292: H3,1.1.1: 1.6.1 Binary compatibility include file svc.h>fo0"#&36814: H4,1.1.1.1: 1.7.3.1 Bit selects>fo #"15864: H3,1.1.1: 1.4.4 Basic Types>fo^$#&84427: H3,1.1.1: 1.5.6 Input arguments>fo%#&84427: H3,1.1.1: 1.5.6 Input arguments>fo&091204: TableTitle: Table11: Mapping data types>foN'#&84427: H3,1.1.1: 1.5.6 Input arguments>\Z?H(-78681: x.Annex.Heading: Annex A Include files>fo #[88142: x.Annex.H2,A.1.1: A.7.5 Allocating actual arguments for SystemVerilog-specific types>fo#Z44514: x.Annex.H2,A.1.1: A.10.11 Example 6 binary compatible calls of exported functions>foM#Z44514: x.Annex.H2,A.1.1: A.10.11 Example 6 binary compatible calls of exported functions-<$lastpagenum><$monthname> <$daynum>, <$year>"<$monthnum>/<$daynum>/<$shortyear>;<$monthname> <$daynum>, <$year> <$hour>:<$minute00> <$ampm>"<$monthnum>/<$daynum>/<$shortyear><$monthname> <$daynum>, <$year>"<$monthnum>/<$daynum>/<$shortyear> <$fullfilename> <$filename> <$paratext[ChapterTitle]> <$paratext[SectionTitle]> <$curpagenum> <$paranumonly[Chapter]><$paranum[Chapter]> (continued)+ (Sheet <$tblsheetnum> of <$tblsheetcount>)Heading & Page<$paratext> on page<$pagenum>Pagepage<$pagenum>See Heading & Page%See <$paratext> on page<$pagenum>. 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URe1370 Trancas Street #163 teNapa, CA 94558 vePhone: (707) 251-9977 weFax: (707) 251-9877 e ue %cAll rights reserved. No part of this document may be reproduced or distributed in any medium whatP`EZsoever to any third parties without prior written consent of Accellera Organization, Inc. UBIJ  h  h h…d `U$ fU$ l U$ U$ e Accellera Qm?NSystemVerilog 3.1/draft 2OExtensions to Verilog-2001 d$ UHˆUHˆ""}` ... `} `... `} M UTUTh?qExample 6 binary compatible calls of exported functions gC rThis example demonstrates the source compatibility include file svc_src.hy is not needed if a C function 0Nkdynamically allocates the data structure for simulator representation of a packed array to be passed to an @!exported SystemVerilog function. mn`SystemVerilog: (x` ,`export a.b.c.myfunc; C`... D`3function void myfunc (output logic [31:0] r); ... E`... F`C: G` H`#include "svc.h" I`Cextern void myfunc (svLogicPackedArrRef r); /* exported from SV */ J` K`$/* output logic packed 32-bits */ L`... M`5svLogicVec32 my_r[SVg_CANONICAL_SIZE(32)]; Y`*/* my array, canonical representation */ N` Z`N/* allocate memory for logic packed 32-bits in simulator's representation */ O`svLogicPackedArrRef r = Q`;(svLogicPackedArrRef)malloc(svSizeOfLogicPackedArr(32)); R` myfunc(r); S`/* canonical <-- actual */ U`svGetLogicVec32(my_r, r, 32); T`>/* will use only the canonical representation from now on */ V`$free(r); /* don't need any more */ W`... WX` UHˆUHˆ6ldӒ ! HN`@ӓ HN`@HRHRFootnote Hq<@`@Ӕ Hq<@`@HzHz Single LineH'ӕ Footnote$Ӗ $% HUHˆzD..=2UTUT(k UR@DirectC C-layer U UTUP` Overview `%IplThe DirectC interface allows direct function calls from the other language on either side of the interface: aZ0mfunctions implemented in C can be called from SystemVerilog; such functions are referred to as external +fPfunctions. c%x0dfunctions implemented in SystemVerilog and specified in export declarations in SystemVerilog can be POcalled from C; such functions are referred to as exported functions. `0oThis section describes the C-layer of the DirectC Interface and applies to calls from either direction: C funcP^tions called from SystemVerilog code and exported SystemVerilog functions called from C code. h jThe SystemVerilog DirectC Interface supports only SystemVerilog data types, which are the sole data types 0Ūothat can cross the boundary between SystemVerilog and a foreign language in either direction (i.e., when a forueign function is called from SystemVerilog code or an exported SystemVerilog function is called from vay for@meign code). On the other hand, the data types used in C code shall be C types; hence, the duality of types. v mA value that is passed through the DirectC Interface is specified in SystemVerilog code as a value of System0qVerilog type, while the same value shall be specified in C code as a value of C type. Therefore, passing a value lthrough the DirectC Interface takes a pair of matching type definitions: the SystemVerilog definition and C @ definition. *& mIt is the users responsibility to provide these matching definitions. A tool (such as the SystemVerilog com01rpiler) can facilitate this by generating C type definitions for the SystemVerilog definitions used in the DirectC @/interface for external and exported functions. wQ fSome SystemVerilog types are directly compatible with C types; defining a matching C type for them is 0\lstraightforward. There are, however, SystemVerilog-specific types, namely packed types (arrays, structures, mand unions), 2-state or 4-state, which have no natural correspondence in C. DirectC does not require any parkticular representation of such types and does not impose any restrictions on SystemVerilog implementation. xThis allows implementors to choosey the layout and representation of packed types that best suits their simula@tion performance. x0{While not specifying the actual representation of packed types, this C-layer interface defines ay canonical repre0rsentation of packed 2-state and 4-state arrays. This canonical representation is actually based on Verilog legacy {Programming Language Interfaces (PLIs) avaluey/bvaluey representation of 4-state vectors. Library funcqtions provide the translation between the representation used in a simulator and the canonical representation of qpacked arrays. There are also functions for bit selects and limited part selects for packed arrays, which do not @1require the use of the canonical representation. z骆 gFormal arguments in SystemVerilog can be specified as open arrays solely in the external declarations; 0uexported SystemVerilog functions can not have formal arguments specified as open arraysy. A formal argument uis an topen arrayy when a range of one or more of its dimensions is unspecified (denoted in SystemVerilog by vusing square brackets ([]y)). This is solely a relaxation of the argument-matching rules. An actual argument qshall match the formal one regardless of the range(s) for its corresponding dimension(s), which facilitates writ@Sing a more general C code that can handle SystemVerilog arrays of different sizes. 5 zThe C-layer of the DirectC Interface basically uses normalized ranges. tNormalized rangesy mean -1:0]y p@rindexing for the packed part (packed arrays are restricted to one dimension) and [0:n-1]y indexing for a kdimension in the unpacked part of an array. Normalized ranges are used for the canonical representation of packed arrays in Cy and for System Verilog arrays passed as actual arguments to Cy, with the exception of the mactual arguments for open arrays. The elements of an open array can be accessed in C by using the same range pof indices as defined in System Verilog for the actual argument for that open array and the same indexing as in @SystemVerilog. UHˆ(UHˆW lӜHZӝ ! TableFootnote EGVR`@Ӟ  EGVR`@EPoEPo TableFootnotedV##$$W"$$v$$l $$X"$$-%y#-z "'8=@EHKNQUYdhlptx| !$'*-03:W2BmRSTUVW }$ Z"*$ $W eHTML Mapping Table } \" $W e } ^" $W e }2 `"2 $W e }_ b"_ $W e }$C.d"%+$C.$W  eFrameMaker Source Item }C~f"*-C~$W  e HTML Item }C6h"C6$W  e }2C-.j"+.2C-.$  %Include PEAuto# }_C?.l"-0_C?.$W  e Comments }$Sn"$S$W  e }SHp".1SH$W  eElement }S6r"04S6$  %New Web PEPage? }2S-t"2S-$W  e }_S?v"_S?$W  e }$qx"15$q$W  eP:Body }qHz"46qH$W  eP }q6|"57q6$W  eN }2q-~"682q-$W  eN }_q?р"79_q?$W  e }$,т"8:$,$W  e P:Bulleted }H,ф"9;H,,$  eLI e Parent = UL Qe Depth = 0 }6,ш":<6,$W  eN }2-,ъ";=2-,$W!  eN }_?,ь"<>_?,$W"  e }$ю"=?$$W#  e P:CellBody }Hѐ">@H$W$  eP }6ђ"?A6$W%  eN }2-є"@B2-$W&  eN }_?і"AC_?$W'  e }$ј"BD$$W(  eP:CellHeading }Hњ"CEH$W)  eP }6ќ"DF6$W*  eN }2-ў"EG2-$W+  eN }_?Ѡ"FH_?$W,  e }$Ѣ"GI$$W-  e P:Footnote }HѤ"HJH$W.  eP }6Ѧ"IK6$W/  eN }2-Ѩ"JL2-$W0  eN }_?Ѫ"KM_?$W1  e }$Ѭ"LN$$ W2  e P:Heading1 }HѮ"MOH$ W3  eH* }6Ѱ"NP6$ W4  eN }2-Ѳ"OQ2-$ W5  eN }_?Ѵ"PR_?$ W6  e }$Ѷ"QS$$ W7  e P:Heading2 }HѸ"RTH$ W8  eH* }6Ѻ"SX6$ W9  eN d}WW UHˆ}UUHˆ†D,,W| gFunction arguments are generally passed by some form of a reference or by value. All formal arguments, 0pexcept open arrays, are passed by direct reference or value, and, therefore, are directly accessible in C code. rOnly small values of SystemVerilog input arguments (see sectionA.7.7) are passed by value. Formal argusments declared in SystemVerilog as open arrays are passed by a handle (type svHandley) and are accessible @Nvia library functions. Array-querying functions are provided for open arrays. ~G qDepending on the data types used for the external (or exported) functions, either binary level or C-source level 0Rncompatibility is granted. Binary level is granted for all data types that do not mix SystemVerilog packed and lunpacked types and for open arrays which can have both packed and unpacked parts. If a data type that mixes iSystemVerilog packed and unpacked types is used, then the C code needs to be re-compiled using the imple@9mentation -dependent definitions provided by the vendor. / wThe C-layer of the DirectC Interface provides two include files. The main include file, svc.hy, is implementa0qtion-independent and defines the canonical representation, all basic types, and all interface functions. The secxond include file, svc_src.hy, defines only the actual representation of packed arrays and, hence, its contents @nare implementation-dependent. Applications that do not need to include this file are binary-level compatible. 0 UTUF`Naming conventions }Ϊ`SAll names introduced by this interface shall conform to the following conventions. }ઙpPAll names defined in this interface are prefixed with sv or SV_y. % sFunction and type names start with svy, followed by initially capitalized words with no separators, e.g., "@svBitPackedArrRefy. &`LNames of symbolic constants start with svy_, e.g., sv_xy. '0Names of macro definitions start with SV_y, followed by all upper-case words separated by a dash (-y), e.g., ,.PSV_CANONICAL_SIZEy. ( UTEU=` Portability )[ mDepending on the data types used for the external (or exported) functions, the C code can be binary-level or 0fksource-level compatible. Applications that do not use SystemVerilog packed types are always binary compatikble. Applications that dont mix SystemVerilog packed and unpacked types in the same data type can be writuten to guarantee vthey binary compatibility. Open arrays with both packed and unpacked parts are also binary @ compatible. , kThe values of SystemVerilog packed types can be accessed via interface functions using the canonical repre0osentation of 2-state and 4-state packed arrays, or directly through pointers using the implementation represenetation. The former mode assures binary level compatibility; the latter one allows for tool-specific, kperformance-oriented tuning of an application, though it also requires recompiling with the implementation-@Mdependent definitions provided by the vendor and shipped with the simulator. - UTU1`Binary compatibility 5徭 qBinary compatibilityy means an application compiled for a given platform shall work with every SystemVerilog @simulator on that platform. 6 UT U-`Source-level compatibility 7! rSource-level compatibilityy means an application needs to be re-compiled for each SystemVerilog simulator and ,@Kimplementation-specific definitions shall be required for the compilation. 8 UTBU)`Include files 9X} oThe C-layer of the DirectC Interface defines two include files corresponding to these two levels of compatibilc|@.ity: svc.hy and svc_src.hy. :x{ pBinary compatibility of an application depends on the data types of the values passed through the interface. If Pƒzxall corresponding type definitions can be written in C without the need to include an svc_src.hy file, then an UHˆ} UUHˆfVVl}2-Ѽ"TY2-$ W:  eN }_?Ѿ"XZ_?$ W;  e }$"Y[$$ W<  eP:HeadingRunIn }H"Z\H$ W>  eH* }6"[]6$ W?  eN }2-"\^2-$ W@  eN }_?"]__?$ WA  e }$ ,"^`$ ,$ WB  e P:Indented } H,"_a H,,$ C  eP De Parent = UL QEe Depth = 0 } 6,"`b 6,$ WF  eN }2 -,"ac2 -,$ WG  eN }_ ?,"bk_ ?,$ WH  e d} ff UHˆ}dUHˆ‡D..f:xapplication is binary compatible. If an svc_src.hy file is required, then the application is not binary compat@>ible and needs to be recompiled for each simulator of choice. " mApplications that pass solely C-compatible data types or standalone packed arrays (both 2-state and 4-state) 0vrequire only an svc.hy file and, therefore, are binary compatible with all simulators. Applications that use jcomplex data types which are constructed of both SystemVerilog packed arrays and C-compatible types, also vrequire an svc_src.hy file and, therefore, are not be binary compatible with all simulators. They are source-@level compatible, however. ="UTdUMhsvc.h include file >y oApplications which use the DirectC interface with C code usually need this main include file. The include file "svc.hy defines the types for canonical representation of 2-state (bity) and 4-state (logicy) values and passing "kreferences to SystemVerilog data objects, provides function headers, and defines a number of helper macros @and constants. l }This document fully defines the svc.hy file. The content of svc.hy does not depend on any particular impleHmentation or platform; all simulators shall use the same file. For more details on svc.hy, see sectionA.8.1. Ϫ`jApplications which only use svc.hy shall be binary-compatible with all SystemVerilog simulators. @"UTUD`svc_src.h include file A vThis is an auxiliary include file. svc_src.hy defines data structures for implementation-specific representa0rtion of 2-state and 4-state SystemVerilog packed arrays. The interface specifies the contents of this file, i.e., lwhat symbols are defined. The actual definitions of those symbols, however, are implementation-specific and @"shall be provided by the vendors. B, wApplications that require an svc_src.hy file are only source-level compatible, i.e., they need to be compiled 7@cwith the version of svc_src.hy provided for a particular implementation of SystemVerilog. C UTMU<`Semantic constraints ucpWThis section defines the semantic constraints of the C-layer of the DirectC Interface. d%x0iFormal and actual arguments of both external functions and exported functions are bound by the principle 0lWhat You Specify Is What You Get. This principle is bounding both for the caller and for the callee, in C ocode and in SystemVerilog code. For the callee, it guarantees the actual arguments are as specifed for the foromal ones. For the caller, it means the function call arguments shall conform with the types of the formal arguP=ments, which might require type-coercion on the caller side. e0iIn SystemVerilog code, the compiler can change the formal arguments of native SystemVerilog function and 0Īhmodify its code accordingly, because of optimizations, compiler pragmas, or command line switches. Simimlarly, a SystemVerilog compiler shall provide any necessary coersions for the actual arguments of every funcotion call. For example, a SystemVerilog compiler might truncate or extend bits of a packed array if the widths P2of the actual and formal arguments are different. f0nThe situation is different for external and exported functions. A SystemVerilog compiler can not modify the C 0lcode or perform any coersion or make any changes whatsover to the formal arguments of an external function. mA C compiler can provide coersion only for C types, but not for SystemVerilog types; while at the same time, mthe SystemVerilog code of an exported function expects the types of arguments to be exactly as declared. The ocaller needs to guarantee this. Thus, if the user passes a 10-bit packed array to SystemVerilog, when a 40-bit marray is expected, the error is not be corrected by the C compiler; although, if the same happened in SystemiVerilog code, the SystemVerilog compiler would handle it correctly by providing coercion and a temporary P variable. D UTYU'`Types of formal arguments n{ kThe principle What You Specify Is What You Get guarantees the types of formal arguments of external funcpyzmtions an actual argument is guaranteed to be of the type specified for the formal argument, with the excepmtion of open arrays (for which unspecified ranges are statically unknown). Formal arguments, other than open UHˆ}dUHˆWBee ld}BB dbii$$hch$$hjj l $$hdh$$h(RiWHBmX }$9"cl$9$ WJ  eP:Mapping Table Cell }9H"km9H$ WK  eP }96"ln96$ WL  eN }29-"mo29-$ WM  eN }_9?"np_9?$ WN  e }$I"oq$I$WO  eP:Mapping Table Title }IH"prIH$WP  eP }I6"qsI6$WQ  eN }2I-"rt2I-$WR  eN }_I?"su_I?$WS  e }$Y,"tv$Y,$WT  e P:Numbered }YH,"uwYH,,$V  eLI We Parent = OL QXe Depth = 0 }Y6,"vxY6,$WY  eN }2Y-,"wy2Y-,$WZ  eN }_Y?,"x_Y?,$W[  e }$b,u{$b,wW\  e P:Numbered1 }bH,uz|bH,,w]  eLI ^e Parent = OL Q_e Depth = 0 }b6,u{}b6,wWa  eN }2b-,u|~2b-,wWb  eN }_b?,u}_b?,wWc  e }$u~$wWd  eP:TableFootnote }HuHwWe  eP }6u6wWf  eN }2-u2-wWg  eN }_? u_?wWi  e }$ u$wWj  e P:TableTitle }HuHwWk  eH* }6u6wWl  eN }2-u2-wWm  eN }_?u _?wWn  e }$u $wWo  eP:Title }Hu HwWp  eH* }6u 6wWq  eN }2-u 2-wWr  eN }_?u _?wWs  e }$ u $wWt  e C:Emphasis }H"uHwWu  eEM }6$u6wW  eN }2-&u2-wW  eN }_?(u_?wW  e }$*u$wW  eC:EquationVariables }H,uHwW  eEM }6.u6wW  eN }2-0u2-wW  eN }_?2u_?wW  e }$4u$wW  eX:Heading & Page }H6uHwW  eHeading }68u6wW  eN }2-:u2-wW  eN }_?<u_?wW  e }$>u$wW  eX:Page }H@uHwW  eHeading }6Bu 6wW  eN }2-Du!2-wW  eN }_?Fu "_?wW  e }$Hu!#$wW  eX:See Heading & Page }HJu"$HwW  e See Also }6Lu#%6wW  eN }2-Nu$&2-wW  eN }_?Pu%'_?wW  e }$Ru&4$wW  e X:Table All }$h fh+$h j W eHeadings Table }h hhh j W e }h jhh j W e }$Cllh(,$Clj %W  eHeading Level }Cunh+-Cuj %W  eParagraph Format }CHph,.CHj %W  e Comments }$Slrh-/$Slj &W  e1 }Suth.0Suj &W eTitle }SHvh/1SHj &W  e }$ilxh02$ilj 'W!  e2 }iuzh13iuj 'W# UTUTe Heading1 }iH|h28iHj 'W&  e }HTu'5HwW  e Table All }6Vu466wW$  eN }2-Xu572-wW'  eN }_?Zu68_?wW(  e }$\u79$wW*  eX:Table Number & Page }H^u8:Hw,  %Table PENumber }6`u9;6wW-  eN }2-bu:<2-wW.  eN }_?du;=_?wW1  e }$B gu<@$B wW2 eHTML Options Table }B iuB wW3 e }hB kuhB wW4 e }$Rmu=C$RwW5  eControl UHˆ}gUHˆ„D--Brarrays, are fully defined by external declaration; they shall have ranges of packed or unpacked arrays exactly as 0rspecified in the external declaration. Only the declaration site (SystemVerilog) of the external function is rele@ vant for such formal arguments. J%0tFormaly arguments defined as open arrays have the size and ranges of the actual argument, i.e., have the ranges 2kof packed or unpacked arrays exactly as that of the actual argument. The unsized ranges of open arrays are @bdetermined at a call site; the rest of type information is specified at the external declaration. y\ wSo, if a formal argument is declared as bit [15:8] b []y, then it is the external declaration which specifies 0gthe formal argument is an unpacked array of packed bit array with bounds 15y to 8y, while the actual argument @Wused at a particular call site defines the bounds for the unpacked part for that call. I"UTUK`input arguments M`ZThe formal arguments specified in SystemVerilog as inputy shall not be modified. N"UTUH`output arguments O qThe initial values of formal arguments specified in SystemVerilog as outputy are undetermined and imple˪@mentation-dependent. P UTUD`AValue changes for output and inout arguments Q zThe SystemVerilog simulator is responsible for handling value changes for outputy and inouty arguments. PrSuch changes shall be detected and handled after vthey control returns from C code to SystemVerilog code. R"UTU@`1context and non-context functions S$ rSome PLI and VPI functions require that the context of their call is known. It takes a special instrumentation of 0/{their call instancesy to provide such context; for example, some variables referring to the current instance or kcurrent task need to be set. To avoid any unnecessary overhead, external function calls in SystemVerilog wcode are not instrumented unless the external function is specified as contexty in its SystemVerilog external @ declaration. )e nFor the sake of simulation performance, an external function call shall not block SystemVerilog compiler opti0ptmizations. An external function not specified as contexty shall not access any data objects from SystemVeroilog other then its actual arguments. Only the actual arguments can be affected (read or written) by its call. Therefore, a call of non-contexty function is not a barrier for optimizations. A contexty function, however, wcan access (read or write) any SystemVerilog data objects by calling PLI/VPI; therefore, a call to a contexty @@function is a barrier for SystemVerilog compiler optimizations. . tOnly the calls of contexty functions are properly instrumented and cause conservative optimizations; there0mfore, only those functions can safely call all functions from other APIs, including PLI and VPI functions or xexported SystemVerilog functions. For functions not specified as contexty, the effects of calling PLI, VPI, or pSystemVerilog functions can be unpredictable and such calls can crash if the callee requires a context that has @not been properly set. [%0External functions shall emove:be non-blocking; they shall ]y complete their execution instantly and take 0szero-simulation time. emove on Dougs request:External functions, whether specified as context or not, Pxshall contain no timing control whatsoever (directly or indirectly) via calling PLI or VPI functions. ]y  U"UTU+`pure functions +/ Only non-void functions with no outputy or inouty arguments can be specified as purey. Functions specified 0:~was purey in their corresponding SystemVerilog external declarations shall have no side effects; their results lneed to depend solely on the values of their input arguments. Calls to such functions can be removed by SysmtemVerilog compiler optimizations or replaced with the values previously computed for the same values of the @input arguments. 0pz`uSpecifically, a purey function is assumed not to directly or indirectly (i.e., by calling other functions): Q*y`perform any file operations UHˆ}gUHˆf\AAl}Rou@DRwW6  eValue }hRHquCEhRHwW7  e Comments }$bsuDF$bwW8  e Image Format }buuEGbwW9  e0001IMAGGIF GIF }hbHwuFHhbHwW:  e }$ryuGI$rwW;  e!Copy Files Imported by Reference }r{uHJrwW<  eN }hrH}uIKhrHwW=  e }$uJL$w W>  eExport Encoding }ҁuKMw W?  e ISO-8859-1 }hH҃uLNhHw W@  e }$҅uMO$w!WA  eCSS Export Encoding }҇uNPw!WB  e ISO-8859-1 }hH҉uOhHw!WC  e }$$ ҌxU$$ z"WD eSystem Macros }$ Ҏx$ z"WE e }$ Ґx$ z"WF e }\$ Ғx\$ z"WG e }$4hҔxQV$4hz#WH  e Macro Name }4hҖxUW4hz#WI  e Replace With }4hҘxVX4hz#WJ  eHead }\4BҚxWY\4Bz#WK  e Comments }$Dh,ҜxXa$Dh,z$WL  e StartOfDoc d}\\ UHˆ}ZUHˆ|D**\+0pread or write anything in the broadest possible meaning, includes i/o, environment variables, objects from %P_the operating system or from the program or other processes, shared memory, sockets, etcy. {`=access any persistent data, like global or static variables. 6 tIf a purey function does not obey the above restrictions, SystemVerilog compiler optimizations can lead to E@Nunexpected behavior, due to eliminated calls or incorrect results being used. < UTWUO`Memory management Xl cThe memory spaces owned and allocated by C code and SystemVerilog code are disjoined. Each side is 0wmresponsible for its own allocated memory. Specifically, C code shall not free the memory allocated by SystemkVerilog code (or the SystemVerilog compiler) nor expect SystemVerilog code to free the memory allocated by nC code (or the C compiler). This does not exclude scenarios in which C code allocates a block of memory, then mpasses a handle (i.e., a pointer) to that block to SystemVerilog code, which in turn calls a C function that @Zdirectly (if it is the standard function freey) or indirectly frees that block. ; rNOTEIn this last scenario, a block of memory is allocated and freed in C code, even when the standard functions "@Lmalloc| and free| are called directly from SystemVerilog code. Y UTUG` Data types {`MThis section defines the data types of the C-layer of the DirectC Interface. Z UTUD` Limitations 1 lPacked arrays can have an arbitrary number of dimensions; though they are eventually always equivalent to a 0#none-dimensional packed array and treated as such. If the packed part of an array in the type of a formal argulment in SystemVerilog is specified as multi-dimensional, the SystemVerilog compiler linearizes it. Although kthe original ranges are generally preserved for open arrays, if the actual argument has a multidimensional @[packed part of the array, the equivalent one-dimensional packed array shall be normalized. EZ`nNOTEThe actual argument can have both packed and unpacked parts of an array; either can be multidimensional. ] UTrU=`2Duality of types: SystemVerilog types vs. C types ^ pA value that crosses the DirectC Interface is specified in SystemVerilog code as a value of SystemVerilog type, 0qwhile the same value shall be specified in C code as a value of C type. Therefore, each data type that is passed nthrough the DirectC Interface requires two matching type definitions: the SystemVerilog definition and C defi@nition. < kThe user needs to provide such matching definitions. Specifically, for each SystemVerilog type used in the 0Ȫoexternal declarations or export declarations in SystemVerilog code, the user shall provide the equivalent type ldefinition in C reflecting the argument passing mode for the particular type of SystemVerilog value and the direction (inputy, outputy, or inouty) of the formal SystemVerilog argument. For values passed by reference, a generic pointer void *y can be used (conveniently typedefyed iny svc.hy ory svc_src.hy) without @0knowing the actual representation of the value. _ UTU1`Data representation ``iDirectC imposes the following additional restrictions on the representation of SystemVerilog data types. d,xcBasic integer and real data types are represented as definedy in msectionA.6.4n. b>`0_V0tHence, an arrays elements, other than scalars or packed arrays, can be accessed from C code yvia pointers @-similarly to doing so for individual values. e hThe layout of unpacked arrays, with the exception of actual arguments passed for formal arguments speci0jfied as open arrays, is the same as used by a C compiler; this includes arrays embedded in structures and @Cany standalone arrays (i.e., those not embedded in any structure). gM iThe natural order of elements for each dimension in the layout of an unpacked array shall be used, i.e., 0Ynelements with lower indices go first. For SystemVerilog range :R]y, the element with SystemVerilog qindex min(L,R)y has the C index 0 and the element with SystemVerilog index max(L,R)y has the C @index abs(L-R)y. i wNOTEThis does not actually impose any restrictions on how unpacked arrays are implemented; it only says an array that 0}does not satisfy this condition shall not be passed as an actual argument for the formal argument which is a sized array; it {can be passed, however, for unsized (i.e., open) array. Therefore, the correctness of an actual argument might be implemenytation-dependent. Nevertheless, an open array provides an implementation-independent solution; this seems to be a reason@able trade-off. %Ǫp>DirectC also supports the following SystemVerilog data types. [ت0tBasic integer and real data types are represented as defined in SystemVerilog LRM sections 3.3 and 3.4.2v; 䪟X"see also sectionA.6.4. \pqThe layout of unpacked structures is same as used by a C compiler (see SystemVerilog LRM section 3.7v). j UT UGhBasic types k(u}TableA1 on page36| defines the mapping between the basic SystemVerilog data types and the corresponding C )types. )@H\**Revise this xref w/ Stu; also check/revise variable settings, etc.** y m) {The representation of SystemVerilog-specific data types like packed bity and logicy arrays is implementa04ntion-dependent and generally transparent to the user. Nevertheless, for the sake of performance, applications mcan be tuned for a specific implementation and make use of the actual representation used by that implementa@Ation; such applications shall not be binary compatible, however. n UT\U=`Normalized ranges oq iPacked arrays are treated as one-dimensional; the unpacked part of an array can have arbitrary number of P|dimensions. tNormalized rangesy mean -1:0]y indexing for the packed part and [0:n-1]y indexing for a UHˆ}%]UHˆ\7^^ld})77 }Dh,ҞxYbDh,z$WM  e }Dh,ҠxacDh,,z$N  % ��<$defaulttitle></P��ETITLE> }\��DB,��Ң�xbd��\��DB,z�$WO  ��e }$ph��Ҥ�xce��$phz�(�WP  ��e EndOfDoc }��ph��Ҧ�xdf����phz�(WQ  ��e }��ph��Ҩ�xeg����phz�(WR  ��e }\��pB��Ҫ�xfh��\��pBz�(WS  ��e }$��h,��Ҭ�xgi��$��h,z�)�WT  ��eStartOfSubDoc }����h,��Ү�xhj������h,z�)WU  ��e }����h,��Ұ�xik������h,,z�)V  ��%<TITLE> ��<$defaulttitle></P��ETITLE> }\����B,��Ҳ�xjl��\����B,z�)WW  ��e }$��h��Ҵ�xkm��$��hz�*�WX  ��e EndOfSubDoc }����h��Ҷ�xln������hz�*WY  ��e }����h��Ҹ�xmo������hz�*WZ  ��e }\����B��Һ�xnp��\����Bz�*W[  ��e }$��h,��Ҽ�xoq��$��h,z�+�W\  ��eStartOfFirstSubDoc }����h,��Ҿ�xpr������h,z�+W]  ��e }����h,���xqs������h,,z�+^  ��%<TITLE> ��<$defaulttitle></P��ETITLE> }\����B,���xrt��\����B,z�+W`  ��e }$��h���xsu��$��hz�,�Wa  ��eEndOfFirstSubDoc }����h���xtv������hz�,Wb  ��e }����h���xuw������hz�,Wc  ��e }\����B���xvx��\����Bz�,Wd  ��e }$��h,���xwy��$��h,z�-�We  ��eStartOfLastSubDoc }����h,���xxz������h,z�-Wf  ��e }����h,���xy{������h,,z�-g  ��%<TITLE> ��<$defaulttitle></P��ETITLE> }\����B,���xz|��\����B,z�-Wh  ��e }$$��h���x{}��$$��hz�.�Wi  ��eEndOfLastSubDoc }��$��h���x|~����$��hz�.Wj  ��e }��$��h���x}����$��hz�.Wk  ��e }\��$��B���x~���\��$��Bz�.Wl  ��e }$:���� ���x��$:���� z �/�Wm ��eCross-Reference Macros }��:���� ���x������:���� z �/Wn ��e }D��:���� ���x����D��:���� z �/Wo ��e }$J�������x���$J����z �0�Wp  ��e Macro Name }��J�������x����J����z �0Wq  ��e Replace With }D��J��?���x��D��J��?z �0Wr  ��e Comments }$Z�������x��$Z����z �1�Ws  ��eHeading }��Z�������x����Z����z �1Wt  ��e <$paratext> }D��Z��?���x ��D��Z��?z �1Wu  ��e }$j�������x ��$j����z �2�Wv  ��e See Also }��j�������x ����j����z �2Ww  ��eSee <$paratext>. }D��j��?���x ��D��j��?z �2Wx  ��e }$z�������x ��$z����z �3�Wy  ��e Table All }��z�������x ����z����z �3z  ��%Table <$paranumonly>, P��E <$paratext> }D��z��?���x ��D��z��?z �3W{  ��e }$�������x��$����z �4�W|  ��e Table Number }���������x��������z �4W~  ��eTable <$paranumonly> }D����?���x���D����?z �4W  ��e }$$�� ���{���$$�� } �5�W� ��eGeneral Macros }v$�� ���{����v$�� } �5W ��e }$�� ���{����$�� } �5W ��e }2��$�� ���{����2��$�� } �5W ��e }$4ev�� �{��$4ev} �6�W  ��e Macro Name }v4ev�� �{��v4ev} �6W  ��e Replace With }4C���{��4C} �6W  ��eHead }2��4Q���{��2��4Q} �6W  ��e Comments }$Dev���{��$Dev} �7�W  ��e }vDev���{��vDev} �7W  ��e }DC���{��DC} �7W  ��e }2��DQ���{��2��DQ} �7W  ��e }$Z�� ���{!��$Z�� } �8�W ��eCharacter Macros }lZ�� ���{����lZ�� } �8W ��e }��Z�� ���{������Z�� } �8W ��e }$jH��!�{"��$jH} �9�W  ��e Character }lj����#�{!#��lj��} �9W  ��e Replace With }��j?��%�{"$����j?} �9W  ��e Comments }$zH��'�{#%��$zH} �:�W  ��e }lz����)�{$&��lz��} �:W  ��e¢ }��z?��+�{%'����z?} �:W  ��e }$��H��-�{&(��$��H} �;�W  ��e }l������/�{')��l����} �;W  ��e© }����?��1�{(*������?} �;W  ��e }$��H��3�{)+��$��H} �<�W  ��e }l������5�{*,��l����} �<W  ��e® }����?��7�{+-������?} �<W  ��e }$��H��9�{,.��$��H} �=�W  ��e }l������;�{-/��l����} �=W  ��e° }����?��=�{.0������?} �=W  ��e }$��H��?�{/1��$��H} �>�W  ��e }l������A�{02��l����} �>W  ��e-- }����?��C�{13������?} �>W  ��e }$��H��E�{24��$��H} �?�W!  ��e }l������G�{35��l����} �?W"  ��e- }����?��I�{4:������?} �?W#  ��e UH��ˆ����}*�`����UH��ˆ��i�L"��� ��(M7����o����ldimension of the unpacked part of an array. Normalized ranges are used for accessing all arguments but open ���@Sarrays. The canonical representation of packed arrays also uses normalized ranges. r UTUR���h@�Mapping between SystemVerilog ranges and normalized ranges s��� kThe SystemVerilog ranges for a formal argument specified as an open array are those of the actual argument 0C����qfor a particular call. Open arrays are accessible, however, by using their original ranges and the same indexing ���@as in the SystemVerilog code. tc��� oFor all other types of arguments, i.e., all arguments but open arrays, the SystemVerilog ranges are defined in 0n����ithe corresponding SystemVerilog external or export declaration. Normalized ranges are used for accessing ����gsuch arguments in C code. The mapping between SystemVerilog ranges and normalized ranges is defined as ���@ follows. u��� _If a packed part of an array has more than one dimension, it is linearized as specified by the ���P8equivalence of packed types (��see section ??��y). v��� pA packed array of range ��:R]��y is normalized as ��bs(L-R):0]��y; its most significant bit has a ê���@\normalized index ��abs(L-R)��y and its least significant bit has a normalized index 0. pת��� iThe natural order of elements for each dimension in the layout of an unpacked array shall be used, i.e., 0㪚����`elements with lower indices go first. For SystemVerilog range ��:R]��y, the element with ����bSystemVerilog index ��min(L,R)��y has the C index 0 and the element with SystemVerilog index "���@2max(L,R)��y has the C index ��abs(L-R)��y. x��� sNOTEThe above range mapping from SystemVerilog to C applies to calls made in both directions, i.e., SystemVerilog-���@)calls to C and C-calls to SystemVerilog. y3���0nFor example, if ��logic [2:3][1:3][2:0] b [1:10] ��[31:0]��y is used in SystemVerilog, it needs to be >����kdefined in C as if it were declared in SystemVerilog in the following normalized form: ��logic [17:0] b "���P[0:9] ��[31:0]��y. z UT[U>���`*Canonical representation of packed arrays qp��� uThe DirectC interface defines the canonical representation of packed 2-state (type ��svBitVec32��y) and 4-state {����rarrays (type ��svLogicVec32��y). This canonical representation is actually based on the Verilog legacy PLIs "����zavalue��y/��bvalue��y representation of 4-state vectors. Library functions provide the translation between the rep���@Sresentation used in a simulator and the canonical representation of packed arrays. T��� sA packed array is represented as an array of one or more elements (of type ��svBitVec32��y for 2-state values 0����uand ��svLogicVec32��y for 4-state values), each element representing a group of 32 bits.The first element of an ����qarray contains the 32 least-significant bits, next element contains the 32 more-significant bits, and so on. The ����llast element may contain a number of unused bits. The contents of these unused bits is undetermined and the ���@guser is responsible for the masking or the sign extension (depending on the sign) for the unused bits. QW窉��@h�TableA2 on page37� defines the encoding used for a packed ��logic��y array represented as ��svLogicVec32��y. � UH��ˆ����},�`����UH��ˆ���_C66 ����l���}${l��~�h39��${lj �A�W)  ��e3 }��{u��Ӏ�h8=����{uj �AW+  ��e Heading2 }$��H��K�{5;��$��H} �@�W$  ��e }l������M�{:<��l����} �@W0  ��e... }����?��O�{;�������?} �@W1  ��e }��{H��ӂ�h9>����{Hj �AW_  ��e }$l��ӄ�h=?��$lj �B�W.  ��e4 }��u��ӆ�h>@����uj �BW/  ��e HeadingRunIn }��H��ӈ�h?P����Hj �BW3  ��e ��d������}0��������CC�������� UH��ˆ����}1�A����UH��ˆ��w�D+���+����C����} UTUT���`Argument passing modes c���`YThis section defines the ways to pass arguments in the C-layer of the DirectC Interface. ~ UTUQ���` Overview P%D���0sExternal��y function arguments are generally passed by some form of a reference, with the exception of small val2O���wues of SystemVerilog input arguments (see �sectionA.7.7�), which are passed by value. Similarly, the function ���@Zresult, which is restricted to small values, is passed by value, i.e., directly returned. �o��0rThe��y Actual arguments passed by reference typically are passed without changing their representation from the z���@mone used by a simulator. There is no inherent copying of arguments (other than any resulting from coercing). ��0qThe��y Access to packed arrays via the canonical representation involves copying arguments and does incur some 2����qoverhead, however. Alternatively, for the sake of performance the application can be tuned for a particular tool ����land access the packed arrays directly through pointers using implementation representation, which could com���@promise binary compatibility. {���`{NOTEThis provides some degree of flexibility and allows the user to control the trade-off of performance vs. portability. &ݪ��� lFormal arguments, except open arrays, are passed by direct reference or value, and, therefore, are directly 誛����maccessible in C code. Formal arguments declared in SystemVerilog as open arrays are passed by a handle (type "���@9svHandle��y) and are accessible via library functions.  UTUC���`'Calling SystemVerilog functions from C ��� lThere is no difference in argument passing between calls from SystemVerilog to C and calls from C to System0%����jVerilog. Functions exported from SystemVerilog can not have open arrays as arguments. Otherwise, the same ����ltypes of formal arguments can be declared in SystemVerilog for exported functions and external functions. A ����lfunction exported from SystemVerilog shall have the same function header in C as the external function with ����nthe same function result type and same formal argument list. In the case of arguments passed by reference, an ����lactual argument to SystemVerilog function called from C shall be allocated using the same layout of data as ���uSystemVerilog uses for that type of argument; the caller is responsible for the allocation. ��It can be done with %���Xypreserving the binary compatibility, see ��y�psectionA.7.5�o�� and ��y�sectionA.10.11�r��.��  UTyU9���`Argument passing by value ���(yOnly small values of formal input arguments (see �sectionA.7.7�) are passed by value. Function results are also 0����pdirectly passed by value. The user needs to provide the C-type equivalent to the SystemVerilog type of a formal ���@,argument if an argument is passed by value.  UTU4���`Argument passing by reference  ˪��� mFor arguments passed by reference, their original simulator-defined representation shall be used and a refer0֪����pence (a pointer) to the actual data object is passed. The actual argument is usually allocated by a caller. The ����ocaller can also pass over a reference to the object already allocated somewhere else, for example, its own for���@"mal argument passed by reference.  ��0 If an argument of type ��T��y is passed by reference, the formal argument shall be of ��vthe��y type ��T*��y. However, packed  ����xarrays can be also passed using generic pointers ��void*��y (��typedef��yed accordingly to ��svBitPackedAr"���@-rRef��y or ��svLogicPackedArrRef��y).  UT)U+���hB�lAllocating actual arguments for SystemVerilog-specific types  >��� pThis is relevant only for calling (exported) SystemVerilog functions from C code. The caller is responsible for I~���@>allocating the actual arguments that are passed by reference. %^}��0yStatic��y allocation requires ��vthe��y knowledge of the relevant data type. If such a type involves SystemVerilog ri|����wpacked arrays, their actual representation needs to be known to C code; thus, the file ��svc_src.h��y needs to be ���@Uincluded, which makes the C code implementation-dependent and not binary compatible. UH��ˆ����}3�A����UH��ˆ���7FBB����l�����d������}7��������FF�������� UH��ˆ����}8�D����UH��ˆ��€�D+���+����F ������0rSometimes ��vthe��y binary compatibility can be achieved by using dynamic allocation functions. The functions "����hsvSizeOfLogicPackedArr()��y and ��svSizeOfBitPackedArr()��y provide the size of the actual repre"����lsentation of a packed array, which can be used for the dynamic allocation of an actual argument without com���promising the portability (��see��y �sectionA.10.11�). Such a technique does not work if a packed array is a part of ���@another type.  UTDUO���`6Argument passing by ��sv_handle�� - open arrays lY��� oArguments specified as open (unsized) arrays are always passed by a handle, regardless of direction of the Sys0d����otemVerilog formal argument, and are accessible via library functions. The actual implementation of a handle is ����{simulator-specific and transparent to the user. A handle is represented by the generic pointer ��void *��y (��type"����def��yed to ��sv_handle��y). Arguments passed by handle shall always have a ��const��y qualifier, because the user ���@+shall not modify the contents of a handle. "UTUH���h�input�� arguments ���`Dinput��y arguments shall always have a ��const��y qualifier. ��� oinput��y arguments, with the exception of open arrays, are passed by value or by reference, depending on the ̪����lsize. Small values of formal input arguments are passed by value. The following data types are considered ���@ small��y: "誘���`pchar��y, ��byte��y, ��shortint��y, ��int��y, ��longint��y, ��real��y, ��shortreal ���`handle��y, ��string ��0bit��y (i.e., 2-state) packed arrays up to ��64��y ��reviously 32]��y -bit (canonical representation shall be used, like ����for a function result). "6��g[There is a problem here: int is the same as svBitVec32, long long is not the same as svBitVec32[2], ��hso how to return a value in the canonical representation as a function result, if this value is between ��P33 and 64 bits?]��  "R���`=input��y arguments of other types are passed by reference. g��� �If an ��input��y argument is a packed ��bit��y array passed by value, its value shall be represented using the canoni0r����wcal representation ��svBitVec32��y. If the size is smaller than 32 bits, the most significant bits are unused and ����mtheir contents are undetermined. The user is responsible for the masking or the sign extension, depending on ���@the sign, for the unused bits. "UTU6���`*inout�� and ��output�� arguments ���`oinout��y and ��output��y arguments, with the exception of open arrays, are always passed by reference. | UTU3���`Function result ֪���({Types of a function result are restricted to the following SystemVerilog data types (see �TableA1 on page36� for ᪆���@the corresponding C type): "���`char��y, ��byte��y, ��shortint��y, ��int��y, ��longint��y, ��real��y, ��shortreal��y, ��handle��y, ��string #���`+packed ��bit��y arrays up to 32 bits. ���� yIf the function result type is a packed ��bit��y array, the returned value shall be represented using the canonical 0%����|representation ��svBitVec32��y. If a packed ��bit��y array is smaller than 32 bits, the most significant bits are ���@,unused and their contents are undetermined.  UTFU*���h�Include files \~��� vThe C-layer of the DirectC Interface defines two include files. The main include file, ��svc.h��y, is implementapg}����qtion-independent and defines the canonical representation, all basic types, and all interface functions. The sec����nond include file, ��svc_src.h��y, defines only the actual representation of packed arrays and, hence, is ���HEimplementation-dependent. Both files are shown in �Annex B�. UH��ˆ����}:�D����UH��ˆ���CIEE ����l�����d������}>��������II�������� UH��ˆ����}?�G����UH��ˆ��…�D6���6����I ����z|���`[Applications which do not need to include ��svc_src.h��y are binary-level compatible.  UT€U&���h2�Binary compatibility include file ��svc.h a��� oApplications which use the DirectC interface with C code usually need this main include file. The include file "����svc.h��y defines the types for canonical representation of 2-state (��bit��y) and 4-state (��logic��y) values and passing "����kreferences to SystemVerilog data objects, provides function headers, and defines a number of helper macros ���@and constants. ?��� }This document fully defines the ��svc.h��y file. The content of ��svc.h��y does not depend on any particular imple0G���ymentation or platform; all simulators shall use the same file. The following subsections (and �sectionA.9.3.1�) ���@1detail the contents of the ��svc.h��y file. !!e���`-Scalars of type ��bit�� and ��logic  p���`/* canonical representation */  {���` $��`#define sv_00 ��`#define sv_11 ��`:#define sv_z2/* representation of 4-st scalar z */ ��`9#define sv_x3/* representation of 4-st scalar x */ ���` %���`2/* common type for bit and logic scalars. */ ���` typedef unsigned char svScalar; ���` &��`.typedef svScalar svBit;/* scalar */ ��`/typedef svScalar svLogic;/* scalar */ '!���`*Canonical representation of packed arrays  ���`F/* 2-state and 4-state vectors, modelled upon PLIs avalue/bvalue */ ���`=#define ��SV��g_CANONICAL_SIZE(WIDTH) (((WIDTH)+31)>>5) ���` )��`typedef unsigned int  ��`4svBitVec32;/* (a chunk of) packed bit array */ ���` *��pNtypedef struct { unsigned int c; unsigned int d;} ��i/* as in VCS */��g  ��`8svLogicVec32; /* (a chunk of) packed logic array */ |���` !)��� O/* Since the contents of the unused bits is undetermined, the following macros ���@may be handy */ ���`*#define ��SV��g_MASK(N) (~(-1<<(N))) $���` !+�� 2#define ��SV��g_GET_UNSIGNED_BITS(VALUE,N)\ ��@2((N)==32?(VALUE):((VALUE)&��SV��g_MASK(N))) {���` !'�� 0#define ��SV��g_GET_SIGNED_BITS(VALUE,N)\ ���((N)==32?(VALUE):\ ��@Z (((VALUE)&(1<<((N)1)))?((VALUE)|~��SV��g_MASK(N)):((VALUE)&��SV��g_MASK(N)))) %!⪡���h-�Implementation-dependent representation ,���`>/* a handle to a generic object (actually, unsized array) */ ���`typedef void* svHandle; ���` -���`./* reference to a standalone packed array */ ���`"typedef void* svBitPackedArrRef; ���`$typedef void* svLogicPackedArrRef;  ���` .���`O/* total size in bytes of the simulators representation of a packed array */ !���`/* width in bits */ "���`(int svSizeOfLogicPackedArr(int width); A#���`%int svSizeOfBitPackedArr(int width); UH��ˆ����}A�G����UH��ˆ���FLHH����l�����d������}E��������LL�������� UH��ˆ����}F�J����UH��ˆ��„�D4���4����L ����/!o���`OTranslation between the actual representation and the canonical representation |�� I/*functions for translation between the representation actually used by ��@/simulator and the canonical representation */ $���` 1���`'/* s=source, d=destination, w=width */ %���` 2���`/* actual <-- canonical */ &���`Mvoid svPutBitVec32 (svBitPackedArrRef d, const svBitVec32* s, int w); '���`Lvoid svPutLogicVec32 (svLogicPackedArrRef d, const svLogicVec32* s, int w); (���` 3���`/* canonical <-- actual */ )���`Mvoid svGetBitVec32 (svBitVec32* d, const svBitPackedArrRef s, int w); *���`Lvoid svGetLogicVec32 (svLogicVec32* d, const svLogicPackedArrRef s, int w); 4��� pThe above functions copy the whole array in either direction. The user is responsible for providing the correct 0����nwidth and for allocating an array in the canonical representation. The contents of the unused bits is undeter���@mined. 5��� }Although the put/get functionality provided for ��bit��y and ��logic��y packed arrays is sufficient, yet basic, it 0ʪ����lrequires unnecessary copying of the whole packed array when perhaps only some bits are needed. For the sake ��yof ��vthe��y convenience and improved performance, bit selects and limited (up to 32 bits) part selects are also sup���HEported, see �sectionA.9.3.1� and �sectionA.9.3.2�. 7 UTUM���`7Source-level compatibility include file ��svc_src.h 8��� gOnly two symbols are defined: the macros that allow declaring variables to represent the SystemVerilog ���@8packed arrays of type ��bit��y or ��logic��y. 9���` m'���`7#define ��SV��g_BIT_PACKED_ARRAY(WIDTH,NAME) ... +���`8#define ��SV��g_LOGIC_PACKED_ARRAY(WIDTH,NAME) ... :H��0�The actual definitions are implementation-specific. For example, ��vVCS��y ��a SystemVerilog simulator��y might define S���@the later macro as follows. ;]���` ,h���`V#define ��SV��g_LOGIC_PACKED_ARRAY(WIDTH,NAME) \ -���`WsvLogicVec32 NAME [ ��SV��g_CANONICAL_SIZE(WIDTH) ] > UTUG���`*Example 1 binary compatible application ?��`SystemVerilog:  .���` 2��`'typedef struct {int a; int b;} pair;  0���`@extern void foo(input int i1, pair i2, output logic [63:0] o3); 1���` @���`Dexport extern $root.exported_sv_func; // whatever is the syntax ... A���` 3��`Cfunction void exported_sv_func(input int i, output int o [0:7]);  4��`begin ... end endfunction B���`C: /���` n���`#include "svc.h" 5���` C���`%typedef struct {int a; int b;} pair; 6���` D���`Lextern void exported_sv_func(int, int *); /* imported from SystemVerilog */ 7���` E��`Avoid foo(const int i1, const pair *i2, svLogicPackedArrRef o3)  8���`{ A9��`JsvLogicVec32 arr[��SV��g_CANONICAL_SIZE(64)]; /* 2 chunks needed */ UH��ˆ����}H�J����UH��ˆ���IOKK ����l�����d������}L��������OO�������� UH��ˆ����}M�M����UH��ˆ��€�D8���8����O ����:€��` int tab[8]; ;���` F��`printf("%d\n", i1); <��`arr[1].c = i2->a; =��`arr[1].d = 0; >��`arr[2].c = i2->b; ?��`arr[2].d = 0; @��` svPutLogicVec32 (o3, arr, 64); G��` A��`/* call SystemVerilog */  B��`>exported_sv_func(i1, tab); /* tab passed by reference */  C��`...  D���`} H UTUT���`1 Example 2 source-level compatible application I���`SystemVerilog: E���` L��`Ctypedef struct {int a; bit [6:1][1:8] b [65:2]; int c;} triple;  F��`1// troublesome mix of C types and packed arrays H���`!extern void foo(input triple i); I���` J���`Dexport extern $root.exported_sv_func; // whatever is the syntax ... J���` K��`Gfunction void exported_sv_func(input int i, output logic [63:0] o);  K��`begin ... end endfunction L���`C: G(���` o3���`#include "svc.h" N���`#include "svc_src.h" M���` M���`typedef struct { O��` int a; P��`Asv_BIT_PACKED_ARRAY(6*8, b) [64]; /* implementation specific Q��`!representation */ R��` int c;  S��`} triple; T���` N���`?/* Note that b is defined as for bit [6*8-1:0] b [63:0] */ U���` O���`Iextern void exported_sv_func(int, svLogicPackedArrRef); /* imported from V��`%SystemVerilog */ P���` W��`void foo(const triple *i)  X���`{ Y��`int j; Q��`!/* canonical representation */ Z��`KsvBitVec32 arr[��SV��g_CANONICAL_SIZE(6*8)]; /* 6*8 packed bits */ [��`3svLogicVec32 aL[��SV��g_CANONICAL_SIZE(64)]; \���` R��`./* implementation specific representation */ ]��`.��SV��g_LOGIC_PACKED_ARRAY(64, my_tab); ^���` S��` printf("%d %d\n", i->a, i->c); _��`for (j=0; j<64; j++) { `��`:svGetBitVec32(arr, (svBitPackedArrRef)&(i->b[j]), 6*8); a��`... Ab���`} UH��ˆ����}O�M����UH��ˆ���LUNN����l���}$l��ӊ�h@Q��$lj �C�W4  ��e4 }��u��ӌ�hPR����uj �CWF  ��e TableTitle }��H��ӎ�hQ�����Hj �CWG  ��e ��d������}S��������UU�������� UH��ˆ����}T�S����UH��ˆ��†�D/���/����U ����c}���`... d���`/* call SystemVerilog */ 1e�� Hexported_sv_func(2, (svLogicPackedArrRef)&my_tab); /* by reference */  ��@AsvGetLogicVec32(aL, (svLogicPackedArrRef)&my_tab, 64);  ... } T3��� NOTE��a��|, ��b��|, and ��c��| are directly accessed as fields in a structure. In the case of ��b��|, which represents unpacked array of 0=����}packed arrays, the individual element is accessed via the library function ��svGetBitVec32()��|, by passing its address ���@to the function. V UT^UT���`Arrays Wt��� kNormalized ranges are used for accessing SystemVerilog arrays, with the exception of formal arguments spec���@ified as open arrays. X UTUP���`Multidimensional arrays Y���`dPacked arrays shall be one-dimensional. Unpacked arrays can have an arbitrary number of dimensions. Z UTUM���`!Direct access to unpacked arrays [ͪ��� mUnpacked arrays, with the exception of formal arguments specified as open arrays, shall have the same layout ت���H[as used by a C compiler; they are accessed using C indexing (see �sectionA.6.6�). \ UTUI���`5Access to packed arrays via canonical representation ]��� pPacked arrays are accessible via canonical representation; this C-layer interface provides functions for moving 0 ����idata between implementation representation and canonical representation (any necessary conversion is per���~formed on-the-fly (see �sectionA.8.1.3�)), and for bit selects and limited (up to 32-bit) part selects. (Bit selects ���@.do not involve any canonical representation.) _!3���h�Bit selects hI���h|This subsection defines the bit selects portion of the ��svc.h��y file (see �sectionA.8.1� for more details). `S���`  ^���`2/* Packed arrays are assumed to be indexed n-1:0, U���`4where 0 is the index of least significant bit */ f���` a���` /* functions for bit select */ !���` g���`/* s=source, i=bit-index */ h���`9svBit svGetSelectBit(const svBitPackedArrRef s, int i); i���`>svLogic svGetSelectLogic(const svLogicPackedArrRef s, int i); c���`  ���`+/* d=destination, i=bit-index, s=scalar */ j���`;void svPutSelectBit(svBitPackedArrRef d, int i, svBit s); k���`@void svPutSelectLogic(svLogicPackedArrRef d, int i, svLogic s); e!몗���h�Part selects f��� Limited (up to 32-bit) part selects are supported. A ��tpart select��y is a slice of a packed array of types ��bit��y or " ���@@logic��y. Array slices are not supported for unpacked arrays. g!��� qFunctions for part selects only allow access (read/write) to a narrow subrange of up to 32 bits. A canonical rep,���@3resentation shall be used for such narrow vectors. j6���` dA���`/* i���`* functions for part select o���`* l���`8* a narrow (<=32 bits) part select is copied between m���`=* the implementation representation and a single chunk of An���`* canonical representation UH��ˆ����}V�S����UH��ˆ���OXTT ����l�����d������}Z��������XX�������� UH��ˆ����}[�V����UH��ˆ��†�D.���.����X����pƒ���`D* Normalized ranges and indexing [n-1:0] are used for both arrays: b���`K* the array in the implementation representation and the canonical array. h���`* q���`<* s=source, d=destination, i=starting bit index, w=width r���`:* like for variable part selects; limitations: w <= 32 s���`*/ kI��� NOTEFor the sake of symmetry, a canonical representation (i.e., an array) is used both for ��bit��| and ��logic��|, although a S���@Osimpler ��int��| can be used for ��bit��|-part selects (<= 32-bits): zi���`/* canonical <-- actual */ "t���`Jvoid svGetPartSelectBit(svBitVec32* d, const svBitPackedArrRef s, int i, v���` int w); t���`Pvoid svGetPartSelectLogic(svLogicVec32* d, const svLogicPackedArrRef s, int i, w���`"int w); x���` }���`/* actual <-- canonical */ n���`Ivoid svPutPartSelectBit(svBitPackedArrRef d, const svBitVec32 s, int i, ~���`!int w); 0���`Ovoid svPutPartSelectLogic(svLogicPackedArrRef d, const svLogicVec32 s, int i, ���` int w); q UTUT���` Open arrays r��� nFormal arguments specified as open arrays allows passing actual arguments of different sizes (i.e., different 0��vrange and/or different number of elements), which facilitates writing ��va��y more general C code that can handle ����nSystemVerilog arrays of different sizes. The elements of an open array can be accessed in C by using the same ���xrange of indices and the same indexing as in SystemVerilog. Plus, ��inquiries��y about the dimensions and the orig���@Pinal boundaries of SystemVerilog actual argument are supported for open arrays. ^E���pINOTE��Both packed and unpacked array dimensions can be unsized��|. t\��� nAll formal arguments declared in SystemVerilog as open arrays are passed by handle (type ��svHandle��y), 0g����lregardless of the direction of a SystemVerilog formal argument. Such arguments are accessible via interface ���@ functions. u UTUJ���`Actual ranges v��� nThe formal arguments defined as open arrays have the size and ranges of the actual argument, as determined on 0����la per-call basis. The programmer shall always have a choice whether to specify a formal argument as a sized ���@%array or as an open (unsized) array. xĪ��� yIn the former case, all indices are normalized on the C side (i.e., ��0��y and up) and the programmer needs to know 0Ϫ����jthe size of an array and be capable of determining how the ranges of the actual argument map onto C-style ���H&ranges (see �sectionA.6.6�). pꪘ���`fHint:��y programmers may decide to stick to ��:0]name[0:k]��y style ranges in SystemVerilog. y���� pIn the later case, i.e., an open array, individual elements of a packed array are accessible via interface func ���@qtions, which facilitate the SystemVerilog-style of indexing with the original boundaries of the actual argument. { ��� sIf a formal argument is specified as a sized array, then it shall be passed by reference, with no overhead, and is 0+���{directly accessible as a normalized array. If a formal argument is specified as ��an��y open (unsized) array, then it ����nshall be passed by handle, with some overhead, and is mostly indirectly accessible, again with some overhead, ���@6although it retains the original argument boundaries. wW��� tNOTEThis provides some degree of flexibility and allows the programmer to control the trade-off of performance vs. a���@ convenience. W}x���`WThe following example shows the use of sized vs. unsized arrays in SystemVerilog code. UH��ˆ����}]�V����UH��ˆ���U[WW����l�����d������}a��������[[�������� UH��ˆ����}b�Y����UH��ˆ���D0���0����[����~‚���` ���`J// both unpacked arrays are 64 by 8 elements, packed 16-bit each ���`+logic [15: 0] a_64x8 [63:0][7:0]; ���`%logic [31:16] b_64x8 [64:1][-1:-8]; ���` ���`9extern void foo(input logic [] i [][]);  ���`H// 2-dimensional unsized unpacked array of unsized packed logic ����`  ���`Gextern void boo(input logic [31:16] i [64:1][-1:-8]);  ���`D// 2-dimensional sized unpacked array of sized packed logic  ���` ���`foo(a_64x8);  ���`Efoo(b_64x8); // C code may use original ranges [31:16][64:1][-1:-8] ���` ���`Eboo(b_64x8); // C code must use normalized ranges [15:0][0:63][0:7]  UTUT���`Array querying functions ��� hThese functions are modelled upon the SystemVerilog array querying functions and use the same semantics Ǫ���@,(see ��wSystemVerilog 3.0 LRM 16.3��y). ܪ��� lIf the dimension is 0, then the query refers to the packed part (which is one-dimensional) of an array, and 窥���@Adimensions ��> 0��y refer to the unpacked part of an array. ���` ���`,/* h= handle to open array, d=dimension */ ���`&int svLeft(const svHandle h, int d); ���`'int svRight(const svHandle h, int d); ���`%int svLow(const svHandle h, int d); ���`&int svHigh(const svHandle h, int d); ���`+int svIncrement(const svHandle h, int d); ���`(int svLength(const svHandle h, int d); ���`$int svDimensions(const svHandle h);  UT\UN���`Access functions q��� mSimilarly to sized arrays, there are functions for copying data between the simulator representation and the 0|����ocanonical representation and to obtain the actual address of SystemVerilog data object or of an individual ele���@nment of an unpacked array. This information might be useful for simulator-specific tuning of the application.  ���0pDepending on the type of an element of an unpacked array, different access methods shall be used ��when work%���Ping with elements��y. ���`sPacked arrays (��bit��y or ��logic��y) are accessed via copying to or from the canonical representation. ʪ���`hScalars (1-bit value of type ��bit��y or ��logic��y) are accessed (read or written) directly. ��� mOther types of values (e.g., structures) are accessed via generic pointers; a library function calculates an 誚���@?address and the user needs to provide the appropriate casting. ��� mScalars and packed arrays are accessible via pointers only if the implementation supports this functionality 0����m(per array), e.g., one array can be represented in a form that allows such access, while another array might ����kuse a compacted representation which renders this functionality unfeasible (both occurring within the same ���@ simulator).  4��0{SystemVerilog allows arbitrary dimensions and, hence, an arbitrary number of indices. To facilitate this, ��va��y vari0?��|able argument list functions shall be used. For the sake of performance, ��vthe��y specialized versions of all indexing ���@/functions are provided for 1, 2, or 3 indices.  UT\U<���`$Access to the actual representation W q���0yThe following functions provide an actual address of the whole array or of its individual ��elements��y. These funcUH��ˆ����}d�Y����UH��ˆ���XZZ ����l�����d��������������^^�������� UH��ˆ�����\����UH��ˆ���D5���5����^����1|���`?int indx1, int indx2, int indx3); ���` 3���`/* canonical <-- actual */ 4���`Nvoid svGetBitArrElemVec32 (svBitVec32* d, const svHandle s, int indx1, ...); 5���`Ivoid svGetBitArrElem1Vec32(svBitVec32* d, const svHandle s, int indx1); !6�� Qvoid svGetBitArrElem2Vec32(svBitVec32* d, const svHandle s, int indx1, ��@int indx2); r���`=void svGetBitArrElem3Vec32(svBitVec32* d, const svHandle s, 7���`=int indx1, int indx2, int indx3); ���` !8��� Kvoid svGetLogicArrElemVec32 (svLogicVec32* d, const svHandle s, int indx1, ��@...); s���`Mvoid svGetLogicArrElem1Vec32(svLogicVec32* d, const svHandle s, int indx1); 9���`Lvoid svGetLogicArrElem2Vec32(svLogicVec32* d, const svHandle s, int indx1, :���`*int indx2); ;���`Avoid svGetLogicArrElem3Vec32(svLogicVec32* d, const svHandle s, <���`?int indx1, int indx2, int indx3);  ��� oThe above functions copy the whole packed array in either direction. The user is responsible for allocating an ˪���@'array in the canonical representation. ! UTUR���pHAccess to scalar ��elements�� (��bit�� and ��logic��) =��� zAnother group of functions is needed for scalars (i.e., when an element of an array is a simple scalar, ��bit��y, or "���@ logic��y): "���` O���`=svBit svGetBitArrElem (const svHandle s, int indx1, ...); >���`8svBit svGetBitArrElem1(const svHandle s, int indx1); ?���`CsvBit svGetBitArrElem2(const svHandle s, int indx1, int indx2); @���`MsvBit svGetBitArrElem3(const svHandle s, int indx1, int indx2, int indx3); A���` #���`?svLogic svGetLogicArrElem (const svHandle s, int indx1, ...); B���`:svLogic svGetLogicArrElem1(const svHandle s, int indx1); C���`EsvLogic svGetLogicArrElem2(const svHandle s, int indx1, int indx2); D���`OsvLogic svGetLogicArrElem3(const svHandle s, int indx1, int indx2, int indx3); E���` $���`Kvoid svPutLogicArrElem (const svHandle d, svLogic value, int indx1, ...); F���`Fvoid svPutLogicArrElem1(const svHandle d, svLogic value, int indx1); !G��� Evoid svPutLogicArrElem2(const svHandle d, svLogic value, int indx1, ��@int indx2); H���`Pvoid svPutLogicArrElem3(const svHandle d, svLogic value, int indx1, int indx2, I���`$int indx3); J���` %���`Gvoid svPutBitArrElem (const svHandle d, svBit value, int indx1, ...); K���`Bvoid svPutBitArrElem1(const svHandle d, svBit value, int indx1); L���`Mvoid svPutBitArrElem2(const svHandle d, svBit value, int indx1, int indx2); M���`Lvoid svPutBitArrElem3(const svHandle d, svBit value, int indx1, int indx2, N���`"int indx3); ' UT UN���`(Access to array elements of other types (!��� rIf an arrays elements are of a type compatible with C, there is no need to use canonical representation. In such 0,����ssituations, the elements are accessed via pointers, i.e., the actual address of an element shall be computed first ���@-and then used to access the desired element. * UTIUI���`'Example 3 two-dimensional open array +^��`SystemVerilog:  &h���` QUs���`%typedef struct {int i; ... } MyType; UH��ˆ������\����UH��ˆ���3]] ����l�����d��������������`d��������U$�����_�b��U$�����aa ����l��� U$�����_����U$����������`����#�e Accellera Q(�m&�QSystemVerilog 3.1/draft 2�Y  Uw��R���_`d��Uw��R���cc ����l��� Uw��R���_����Uw��R��������b����6��m^�Z#�[Copyright �\2002�] Accellera. All rights reserved.�Running H/F 4� Qs��e UH��ˆ�����_b���UH��ˆ�����ee ����l��� UH��ˆ�����_����UH��ˆ����������d����Wl��e Uw��R��� h��Uw��R���gg ����l��� Uw��R��� ����Uw��R��������f������m^�^#�_Copyright �`2002�a Accellera. All rights reserved.�bRunning H/F 4�c Q��e D�;Hˆ����� fU`�U�D�;Hˆ���U�ii ����l��� D�;Hˆ����� ����D�;Hˆ�������������h�������d������1��������ka�������� ��_���2�j�l����_�����������D�;Hˆ����3�jkna�V�D�;Hˆ���V�mm����l��� D�;Hˆ����4�j����D�;Hˆ�������������l�����U$����5�jlp��U$�����oo����l��� U$����6�j����U$����������n����O��e Accellera QP�m?Extensions to Verilog-2001�PSystemVerilog 3.1/draft 2�d U�w��R��7�jnV��U�w��R���qq����l��� U�w��R��8�j����U�w��R��������p����Q��m^�eRunning H/F 4�fCopyright �g2002�h Accellera. All rights reserved.�i#�j QR��e ��d������N��������ss��������UH��ˆ����O�r����UH��ˆ�����tt ����l��� UH��ˆ����P�r����UH��ˆ����������s����WT��e ��d������S��������vv��������$$������T�u����$$����#yww�����l��� $$������U�u����$$�����������zPv�z "'8=@EHKNQUYdhlptx|� !$'*-03:����d������X��������yy��������$$������Y�x����$$����v|zz����l��� $$������Z�x����$$�������� ���Qy�QUYdhlptx|�  !$'*-03:����d������]��������||��������$$������^�{����$$����y�}}�����l��� $$������_�{����$$�������� ����<|� !$'*-03:�����d������Ӡ� ������� ��������HH��ˆ����ӡ� ~����HH��ˆ�����������l��� HH��ˆ����Ӣ� ~����HH��ˆ��� ��� ��������U�e"<$paranum><$paratext><$pagenum> V�e#<$paranum><$paratext><$pagenum> W�e#<$paranum><$paratext><$pagenum> X�e#<$paranum><$paratext><$pagenum> YZ�e$<$paranum><$paratext><$pagenum> Zb�e#<$paranum><$paratext><$pagenum> [~�e"<$paranum><$paratext><$pagenum> \�e"<$paranum><$paratext><$pagenum> C]��e F��d������У��������\��������U$����Ф����U$���������l��� U$����Х�����U$��������������h��` Accellera Qi��h?�sSystemVerilog 3.1/draft 2�tExtensions to Verilog-2001 Uw��R��Ц�\��Uw��R���[[����l�����d������к��������"�������� ��_���л������_�����������UH��ˆ����м���UH��ˆ����� ����l��� UH��ˆ����н�����UH��ˆ��������������Wf��e U$����о�"��U$�����!! ����l��� UH��ˆ���������UH��ˆ���D4���4�������� |��xtions shall be used for accessing elements of ��vthe��y arrays of types compatible with C. These functions are also ��Ptuseful for ��vthe��y vendors, because they provide access to the actual representation for all types of arrays. ��� nIf the actual layout of the SystemVerilog array passed as an argument for an open unpacked array is different 0�� than the C layout, then it is not ��vbe��y possible to access such ��an��y array as a whole; therefore, the address and size of ���such ��an ��yarray shall be undefined (zero (��0��y), to be exact). Nonetheless, the addresses of individual elements of an ���@!array shall be always supported. R���`{NOTENo specific representation of an array is assumed here; hence, all functions use a generic pointer ��void *��|. h���`M/* a pointer to the actual representation of the whole array of any type */ s���`/* NULL if not in C layout */ ���`%void *svGetArrayPtr(const svHandle); ���` ���`Lint svSizeOfArray(const svHandle); /* total size in bytes or 0 if not in C  ���`0layout */ !���` ���`3/* Return a pointer to an element of the array "���`9or NULL if index outside the range or null pointer */ ���` #���`7void *svGetArrElemPtr(const svHandle, int indx1, ...); ���` $���`A/* specialized versions for 1-, 2- and 3-dimensional arrays: */ %���`4void *svGetArrElemPtr1(const svHandle, int indx1); &���`?void *svGetArrElemPtr2(const svHandle, int indx1, int indx2); '���`Ivoid *svGetArrElemPtr3(const svHandle, int indx1, int indx2, int indx3); #���0yAccess to an individual ��array��y element via pointer makes sense only if the representation of such an element is .����kthe same as it would be for an individual value of the same type. Representation of array elements of type "����scalar��y or ��tpacked value��y is implementation-dependent; the above functions shall return ��NULL��y if the represen���@dtation of the array elements differs from the representation of individual values of the same type. _N���`  UTaUK���p:Access ��to elements�� via canonical representation v���`tThis group of functions is meant for accessing elements which are packed arrays (��bit��y or ��logic��y). ��� oThe following functions copy a single vector from a canonical representation to an element of an open array or 0����oother way round. The element of an array is identified by indices, bound by the ranges of the actual argument, ���@?i.e., the original SystemVerilog ranges are used for indexing. ���` (���`O/* functions for translation between simulator and canonical representations*/ ���`/* s=source, d=destination */ ���`/* actual <-- canonical */ !p�� Lvoid svPutBitArrElemVec32 (const svHandle d, const svBitVec32* s, ��@int indx1, ...); ���`Ovoid svPutBitArrElem1Vec32(const svHandle d, const svBitVec32* s, int indx1); *���`Nvoid svPutBitArrElem2Vec32(const svHandle d, const svBitVec32* s, int indx1, +���`(int indx2); !,��� ovoid svPutBitArrElem3Vec32(const svHandle d, const svBitVec32* s, ���@=int indx1, int indx2, int indx3); ���` 2���`Gvoid svPutLogicArrElemVec32 (const svHandle d, const svLogicVec32* s, -���`/int indx1, ...); !.�� Qvoid svPutLogicArrElem1Vec32(const svHandle d, const svLogicVec32* s, ��@int indx1); q���`Gvoid svPutLogicArrElem2Vec32(const svHandle d, const svLogicVec32* s, /���`5int indx1, int indx2); A0���`Gvoid svPutLogicArrElem3Vec32(const svHandle d, const svLogicVec32* s, UH��ˆ���������UH��ˆ���[^����l���}fW_@ ���]>��fW_@ ^7�D�WL���`SystemVerilog type }6cUC���]��6cUC^7�DWx���`C type }fW_@ ���] ��fW_@ ^7�E�Wy# ���`char }6cUC���]7��6cUC^7�EWz# ���`char U$����п�����U$��������������w���` Accellera Q��h?Extensions to Verilog-2001�SystemVerilog 3.1/draft 2� U�w��R������U�w��R���^^ ����l���}fW_@ ���]8$��fW_@ ^7�G�W}# ���` shortint }6cUC���]#%��6cUC^7�GW~# ���` short int }fW_@ ���]$&��fW_@ ^7�H�W# ���`int }6cUC���]%9��6cUC^7�HW�# ���`int ��d��������������NS��������}U>����/�`�=��U>��6C�F�W-!���h+�~Encoding of bits in ��svLogicVec32 }fW_@ ���]:*��fW_@ ^7�J�W# ���`real }6cUC���])+��6cUC^7�JW# ���`double }fW$_@ ���]*,��fW$_@ ^7�K�W# ���` shortreal }6c$UC���]+-��6c$UC^7�KW# ���`float }fW7_@ ���],.��fW7_@ ^7�L�W# ���`handle }6c7UC���]-/��6c7UC^7�LW# ���`void* }fWJ_@ ���].0��fWJ_@ ^7�M�W # ���`string }6cJUC���]/���6cJUC^7�MW # ���`char* ��d��������������33"�������� UH��ˆ�����1����UH��ˆ���D7���7����3����)~���` ,��`Qextern void foo(input MyType i [][]); /* 2-dimensional unsized unpacked array P���`7of MyType */ Q���` -��`MyType a_10x5 [11:20][6:2];  R���`MyType a_64x8 [64:1][-1:-8]; S���` .��`foo(a_10x5);  T���` foo(a_64x8); /h��` C:  Vr���` W}���`#include "svc.h" 0���` X���`%typedef struct {int i; ... } MyType; Y���` 1���`void foo(const svHandle h) Z���`{ [���`MyType my_value; \���` int i, j; ]���`int lo1 = svLow(h, 1); ^���`int hi1 = svHigh(h, 1); _���`int lo2 = svLow(h, 2); `���`int hi2 = svHigh(h, 2); 2���` a���`#for (i = lo1; i <= hi1; i++) { b���`&for (j = lo2; j <= hi2; j++) { 3���` c���`;my_value = *(MyType *)svGetArrElemPtr2(h, i, j); d���`... e���`;*(MyType *)svGetArrElemPtr2(h, i, j) = my_value; f��`...  g���` } h���` ... i���` } j���`} b���` 5 UTUS���`Example 4 open array 6��`SystemVerilog:  4���` k���`typedef struct { ... } MyType; 7���` l���`8extern void foo(input MyType i [], output MyType o []); 8���` m���`MyType source [11:20]; n���`MyType target [11:20]; 9���` o���`foo(source, target); :%��` C:  p/���` ^:���`#include "svc.h" q���` ;���`typedef struct ... } MyType; r���` <���`2void foo(const svHandle hin, const svHandle hout) As���`{ UH��ˆ�����1����UH��ˆ���^622����l�����d��������������66#�������� UH��ˆ�����4����UH��ˆ��€�D8���8����6����t|���`!int count = svLength(hin, 1); u���`-MyType *s = (MyType *)svGetArrayPtr(hin); v���`.MyType *d = (MyType *)svGetArrayPtr(hout); =���` w���`1if (s && d) { /* both arrays have C layout */ >���` x���`8/* an efficient solution using pointer arithmetic */ y���`while (count--) z���`*d++ = *s++; ?���` {���`/* even more efficient: |���`(memcpy(d, s, svSizeOfArray(hin)); }���`*/ @���` ~���`=} else { /* less efficient yet implementation independent */ A���` ���`int i = svLow(hin, 1); ����`int j = svLow(hout, 1); ���`"while (i <= svHigh(hin, 1)) { ���`2*(MyType *)svGetArrElemPtr1(hout, j++) = ���`<*(MyType *)svGetArrElemPtr1(hin, i++); ���`} ���` B���`} C���` ���`} D UT UT���`% Example 5 access to packed arrays E5���`SystemVerilog: ?���`  J���`&extern void foo(input logic [127:0]); ��`Dextern void boo(input logic [127:0] i []);// open array of 128-bit Fk��` C:   u���`  ���`#include "svc.h"  ���` G���` /* one 128-bit packed vector */  ���`7void foo(const svLogicPackedArrRef packed_vec_128_bit) ���`{ ���`VsvLogicVec32 arr[��SV��g_CANONICAL_SIZE(128)]; /* canonical representation */ H���` ���`2svGetLogicVec32(arr, packed_vec_128_bit, 128); ���`... ���`} I���` ���`+/* open array of 128-bit packed vectors */ ���`void boo(const svHandle h) ���`{ ���` int i; ���`VsvLogicVec32 arr[��SV��g_CANONICAL_SIZE(128)]; /* canonical representation */ J���` ���`3for (i = svLow(h, 1); i <= svHigh(h, 1); i++) { K���` ���`OsvLogicPackedArrRef ptr = (svLogicPackedArrRef)svGetArrElemPtr1(h, i); ���`;/* user need not know the vendor representation! */ L���` A���`(svGetLogicVec32(arr, ptr, 128); UH��ˆ�����4����UH��ˆ���355 ����l���}fW_@ ���] 8��fW_@ ^7�N�W=# ���`byte }6cUC���]7#��6cUC^7�NWo# ���`char }fW_@ �� �]&:��fW_@ ^7�P�Wy# ���`longint }6cUC�� �]9)��6cUC^7�PWz# ���` long long }>����1�`����>��6C�FW/���e }>����3�`����>��6C�FW2���e }NH��5�`(@��NH6C�I�W3���`c }U���]���U^7�O�W!���h#�{Mapping data types�� } ���]���� ^7�OW���e } NH��7�`=A�� NH6C�IW4���`d }UNH��9�`@B��UNH6C�IW5���`Value }eH��;�`AC��eH6C�Q�W7 ���`0 } eH��=�`BD�� eH6C�QW8 ���`0 }UeH��?�`CE��UeH6C�QW9 ���`0 }xH��A�`DF��xH6C�R�W: ���`0 } xH��C�`EG�� xH6C�RW; ���`1 }UxH��E�`FH��UxH6C�RW< ���`1 }‹H��G�`GI��‹H6C�S�W= ���`1 } ‹H��I�`HJ�� ‹H6C�SW> ���`0 }U‹H��K�`IK��U‹H6C�SW? ���`z }žH��M�`JL��žH6C�T�W@ ���`1 } žH��O�`KM�� žH6C�TWA ���`1 }UžH��Q�`L���UžH6C�TWB ���`x ���~���'�O�����~����������Zl��d�����'NQ��Zl��d�����PP ����l��� Zl��d�����'����Zl��d����������O����W��e U$�����'OS��U$�����RR ����l��� U$�����'����U$����������Q����W��e Zw��R���'Q���Zw��R���TT ����l��� Zw��R���'����Zw��R��������S����W"��m^�Running H/F 4�Copyright �2002� Accellera. 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