Section E.6, Text

In E.6.1 Replace

 

            Packed arrays can have an arbitrary number of dimensions; though they are eventually always equivalent to a one-dimensional packed array and treated as such. If the packed part of an array in the type of a formal argument in SystemVerilog is specified as multi-dimensional, the SystemVerilog compiler linearizes it. Although the original ranges are generally preserved for open arrays, if the actual argument has a multidimensional packed part of the array, it shall be normalized into an equivalent one-dimensional packed array.

 

WITH

            Packed arrays can have an arbitrary number of dimensions; though they are eventually always equivalent to a one-dimensional packed array and treated as such. If the packed part of an array in the type of a formal argument in SystemVerilog is specified as multi-dimensional, the SystemVerilog compiler linearizes it. Although the original ranges are generally preserved for open arrays, if the actual argument has a multidimensional packed part of the array, it shall be normalized into an equivalent one-dimensional packed array. (See section E.6.5).

 

In E.6.5 Replace

 

E.6.5 Normalized ranges

 

Packed arrays are treated as one-dimensional; the unpacked part of an array can have an arbitrary number of dimensions. Normalized ranges mean [n-1:0] indexing for the packed part and [0:n-1] indexing for a dimension of the unpacked part of an array. Normalized ranges are used for accessing all arguments but open arrays. The canonical representation of packed arrays also uses normalized ranges.

 

WITH

 

E.6.5 Normalized and linearized ranges

 

Packed arrays are treated as one-dimensional; the unpacked part of an array can have an arbitrary number of dimensions. Normalized ranges mean [n-1:0] indexing for the packed part and [0:n-1] indexing for a dimension of the unpacked part of an array. Normalized ranges are used for accessing all arguments but open arrays. The canonical representation of packed arrays also uses normalized ranges.

 

Linearizing a SystemVerilog array with multiple packed dimensions consists of treating an array with dimension sizes (i, j, k) as if it had a single dimension with size (i * j * k) and had been stored as a 1-dimensional array.  The 1-dimensional array has the same layout as the corresponding multiple dimension array stored in row major order.  User C code can take the original dimensions into account when referencing a linearized array element.  For example, the bit in a SystemVerilog packed 2-state array with dimension sizes (i, j ,k) and a SystemVerilog reference myArray[l][m][n] (where the ranges for l, m and n have been normalized) maps to linearized C array bit (n + (m * k) + (l * j * k)).

 

In E.6.6 Replace

 

E.6.6 Mapping between SystemVerilog ranges and normalized ranges

 

The SystemVerilog ranges for a formal argument specified as an open array are those of the actual argument for a particular call. Open arrays are accessible, however, by using their original ranges and the same indexing as in the SystemVerilog code. For all other types of arguments, i.e., all arguments but open arrays, the SystemVerilog ranges are defined in the corresponding SystemVerilog import or export declaration. Normalized ranges are used for accessing such arguments in C code. The mapping between SystemVerilog ranges and normalized ranges is defined as follows.

 

1) If a packed part of an array has more than one dimension, it is linearized as specified by the equivalence of packed types (see Section 4.2).

 

WITH

 

E.6.6 Mapping between SystemVerilog ranges and C normalized ranges

 

The SystemVerilog ranges for a formal argument specified as an open array are those of the actual argument for a particular call. Open arrays are accessible, however, by using their original ranges and the same indexing as in the SystemVerilog code. For all other types of arguments, i.e., all arguments but open arrays, the SystemVerilog ranges are defined in the corresponding SystemVerilog import or export declaration. Normalized ranges are used for accessing such arguments in C code. In the case of packed arrays, C ranges may also be linearized. The mapping between SystemVerilog ranges and normalized C ranges is defined as follows.

 

1) If a packed part of an array has more than one dimension, it is linearized as specified by the equivalence of packed types (see Section E.6.5 and Section 5.8.1 4.2).

 

In E.10.1 Replace

            Packed arrays shall be one-dimensional. Unpacked arrays can have an arbitrary number of dimensions.

WITH

            Packed arrays shall be one-dimensional. Multiple packed dimensions of a SystemVerilog array are linearized (Section E.6.5). Unpacked arrays can have an arbitrary number of dimensions.