Section 10.3

LRM-14

Changes (change in red):

                                                             

It shall be illegal to call a function with output, inout or ref arguments in an event expression, in an expression within a procedural continuous assignment, or in an expression that is not within a procedural statement. However, a const ref function argument shall be legal in this context. (See section 10.5.2)

 

SystemVerilog allows multiple statements to be written between the function header and endfunction, which means that the begin...end can be omitted. If the begin...end is omitted, statements are executed sequentially, as if they were enclosed in a begin...end group. It is also legal to have no statements at all, in which case the function returns the current value of the implicit variable that has the same name as the function.

Section 10.6

LRM-5

Change to Syntax 10-3 (change in red):

 

dpi_function_proto12, 13 ::= function named_function_proto

named_function_proto

| [ signing ] function_data_type function_identifier ( list_of_dpi_proto_formals )

LRM-17

Change to Syntax 10-3 (change in red):

 

list_of_dpi_proto_formals ::=

[ { attribute_instance } dpi_proto_formal { , { attribute_instance } dpi_proto_formal } ]

 

dpi_proto_formal ::=

data_type [ port_identifier dpi_dimension { , port_identifier dpi_dimension } ]