Binding of a module instance or an interface instance works the
same way as described for programs above.
interface range (input clk,enable, input int minval,expr);
property crange_en;
@(posedge clk) enable |-> (minval <= expr);
endproperty
range_chk: assert property (crange_en);
endinteface
bind
cr_unit range r1(c_clk,c_en,v_low,(in1&&in2));
In this example, interface range is instantiated in the module cr_unit. Effectively, every instance of module cr_unit shall contain the interface instance r1.
Where:
— cpu1 is the name of module
instance (cpu1
is an instance of module of module cpu).
— fpu_props is the name of the
program containing properties.
— fpu_rules_1 is the program instance
name.
— Ports (a, b,c) get
bound to signals (a,b,c) of module instance cpu1.
— Only the
cpu1 instance
of cpu gets the properties.
By binding a program to a module or an instance, the
program becomes part of the bound object. The names of assertion related
declarations can be referenced using the SystemVerilog hierarchical naming
conventions.