Section 18.3

LRM-26

Change Syntax 18-1 (change in red):

module_declaration ::=

module_nonansi_header [ timeunits_declaration ] { module_item }

endmodule [ : module_identifier ]

| module_ansi_header [ timeunits_declaration ] { non_port_module_item }

endmodule [ : module_identifier ]

| { attribute_instance } module_keyword [ lifetime ] module_identifier ( .* ) ;

[ timeunits_declaration ] { module_item } endmodule [ : module_identifier ]

| extern module_nonansi_header

| extern module_ansi_header

module_nonansi_header ::=

{ attribute_instance } module_keyword [ lifetime ] module_identifier [ parameter_port_list ]

list_of_ports ;

module_ansi_header ::=

{ attribute_instance } module_keyword [ lifetime ] module_identifier [ parameter_port_list ]

[ list_of_port_declarations ] ;

module_keyword ::= module | macromodule

timeunits_declaration ::=

timeunit time_literal ;

| timeprecision time_literal ;

| timeunit time_literal ;

timeprecision time_literal ;

| timeprecision time_literal ;

timeunit time_literal ;

Section 18.6 (new)

LRM-32

Add the new section (renumber current Section 18.6 and beyond) (change in red):

18.6 List of Port expressions

Verilog 1364-2001 created a list_of_port_declarations alternate style which minimized the duplication of data used to specify the ports of a module. SystemVerilog adds add an explicitly named port declaration to that style, allowing elements of arrays and structures, concatenations of elements, or aggregate expressions of elements declared in a module, interface or program to be specified on the port list.

Like explicitly named ports in a module port declaration, port identifiers exist in their own namespace for each port list. When port item is just a simple port identifier, that identifier is used as both a reference to an interface item and a port identifier. Once a port identifier has been defined, there shall not be another port definition with this same name.

For example:

module mymod(

output .P1(r[3:0]),

output .P2(r[7:4]),

ref .Y(x),

input bit R);

logic [7:0] r;

int x;

…

endmodule

The self-determined type of the port expression becomes the type for the port. If the port expression is to be an aggregate expression, then a cast must be used since self-determined aggregate expressions are not allowed. The port_expression must resolve to a legal expression for type of module port (See section 18.8 – Port Connection Rules). The port expression is optional because ports can be defined that do not connect to anything internal to the port.