Section 19.4.4 (New)

LRM-32

Add new section 19.4.4 (change in red):

19.4.4 Modport expressions

A modport expression allows elements of arrays and structures, concatenations of elements, aggregate expressions of elements declared in an interface to be included in a modport list. This modport expression is explicitly named with a port identifier, visible only through the modport connection.

Like explicitly named ports in a module port declaration, port identifiers exist in their own namespace for each modport list. When modport item is just a simple port identifier, that identifier is used as both a reference to an interface item and a port identifier. Once a port identifier has been defined, there shall not be another port definition with this same name.

For example:

 

interface I;

logic [7:0] r;

const int x=1;

bit R;

modport A (output .P(r[3:0]), input .Q(x), R);

modport B (output .P(r[7:4]), input .Q(2), R);

endinterface

 

module M ( interface i);,

initial i.P = i.Q;

endmodule

 

module top;

   I i1;

  M u1 (i1.A);

  M u2 (i1.B);

  initial #1 $display("%b", i1.r);     // displays 00010010

endmodule

The self-determined type of the port expression becomes the type for the port. If the port expression is to be an aggregate expression, then a cast must be used since self-determined aggregate expressions are not allowed. The port_expression must resolve to a legal expression for type of module port (See section 18.8 – Port Connection Rules). In the example above, the Q port could not be an output or inout because the port expression is a constant. The port expression is optional because ports can be defined that do not connect to anything internal to the port.

Section 19.5 (New)

LRM-6

Add new section 19.5 (and renumber 19.6, 19.7 to 19.7, 19.8) (change in red):

 

19.5 Interfaces and specify blocks

 

The specify block is used to describe various paths across a module and perform timing checks to ensure that events occurring at the module inputs satisfy the timing constraints of the device described by the module. The module paths are from module input ports to output ports and the timing checks are relative to the module inputs. The specify block refers to these ports as terminal descriptor. Module inout ports may function as either an input or output terminal. When one of the port instances is an interface, each signal in the interface becomes an available terminal, with the default direction as defined for an interface, or as restricted by a modport. A ref port may not be used as a terminal in a specify block.

 

The following shows an example of using interfaces together with a specify block:

 

interface itf;

logic c,q,d;

modport flop(input c,d,output q);

endinterface

module dtype(itf.flop ch);

always_ff @(posedge ch.c) ch.q<=ch.d;

specify

   ( posedge ch.c => (ch.q+:ch.d)) = (5,6);

   $setup( ch.d, posedge ch.c, 1 );

endspecify

endmodule

Section 19.7

LRM-3

Change (change in red):

 

interface simple_bus #(parameter AWIDTH = 8, DWIDTH = 8;)

(input bit clk); // Define the interface