Section 3.2

LRM-35

Change in Syntax 3-1 (change in red):

struct_union_member ::= { attribute_instance } data_type list_of_variable_identifiers_or_assignments variable_declaration ;

Section 3.3

LRM-9

Change in Table 3.1 (change in red):

logic

4-state SystemVerilog data type, user-defined vector size with different use rules from reg

Section 3.10.3

LRM-25

Changes (change in red):

SystemVerilog enumerated types are strongly typed, thus, a variable of type enum cannot be directly assigned a value that lies outside the enumeration set unless an explicit cast is used, or unless the enum variable is a member of a union. This is a powerful type-checking aid that prevents users from accidentally assigning nonexistent values to variables of an enumerate type. This restriction only applies to an enumeration that is explicitly declared as a type. The enumeration values can still be used as constants in expressions, and the results can be assigned to any variable of a compatible integral type.

Section 3.10.4 (new)

LRM-25

Add new section 3.10.4 and renumber existing 3.10.4 to 3.10.5 (change in red):

3.10.4 Enumerated types in comparison expressions

The result of any operation on an enumeration variable after the variable has been assigned an out of range value shall be undefined.

Section 3.11

LRM-35

Change in Syntax 3-4 (change in red):

struct_union_member ::= { attribute_instance } data_type list_of_variable_identifiers_or_assignments variable_declaration ;

Section 3.12

LRM-34

Changes in Syntax 3-5 (change in red):

class_declaration ::=

{ attribute_instance } [ virtual ] class [ lifetime ] class_identifier [ parameter_port_list ]

[ extends class_identifier [parameter_value_assignment ] ] ; [ timeunits_declaration ] { class_item }

endclass [ : class_identifier]

Section 3.15

LRM-25

Changes (change in red):

This example assigns the expression (5 => black) to the enumerated type. Without $cast, or the static compile-time cast described below, this type of assignment is illegal.