Section 5.1

LRM-21

Change (change in red):

C constants are either literals, macros or enumerations. There is also a const, keyword but it is not enforced in C.

LRM-20

Change (change in red):

Verilog 2001 constants are literals, parameters, genvars, localparams and specparams. Verilog 2001 also has variables and nets. Variables must be written by procedural statements, and nets must be written by continuous assignments or ports.

LRM-19

Change (change in red):

A variable can be static (storage allocated on instantiation and never de-allocated) or automatic (stack storage allocated on entry to a task, function or named block and de-allocated on exit). C has the keywords static and auto. SystemVerilog follows Verilog in respect of the static default storage class, with automatic tasks and functions, but allows static to override a default of automatic for a particular variable in such tasks and functions.

Section 5.2

LRM-22, LRM-35

Change (in Syntax 5-1) (change in red):

data_declaration ::=

[lifetime] variable_declaration

| constant_declaration

| type_declaration

block_variable_declaration ::=

[ lifetime ] data_type list_of_variable_identifiers ;

| [ lifetime ] data_type list_of_variable_decl_assignments ;

LRM-35

Change (in Syntax 5-1) (change in red):

variable_declaration ::=

[ lifetime ] data_type list_of_variable_identifiers_or_assignments list_of_variable_decl_assignments ;

Section 5.4

LRM-28

Changes (change in red):

A variable can be declared with an initializer, for example: which must be a constant expression.

Section 5.5

LRM-29

Changes (change in red):

Data declared in a static task, function or block defaults to a static lifetime and a local scope. If an initializer is used, the keyword static must be specified to make the code clearer.

LRM-36

Changes (change in red):

Note that automatic or dynamic variables cannot be used to trigger an event expression or be written with a nonblocking or continuous assignments. Automatic variables and dynamic constructs—objects handles, dynamic arrays, associative arrays, strings, and event variables—are limited to the procedural context.

Section 5.6

LRM-4

Change (change in red):

In SystemVerilog, all variables can now be written either by one continuous assignment, or by one or more procedural statements, including procedural continuous assignments. It shall be an error to have multiple continuous assignments or a mixture of procedural and continuous assignments writing to any term in the expansion of a written longest static prefix of a logic variable (See Section 9.2.1 for the definition of the expansion of a longest static prefix) the same variable. All data types can write through a port.