Section 7.10.1 (new)

LRM-23

Add to new Section 7.10.1 (change in red):

7.10.1 Built-in namespace

 

SystemVerilog provides a built-in namespace that contains types (e.g., classes), tasks and functions. The built-in namespace resides at the top of the hierarchy. Users may not insert additional declarations into the built-in namespace. The declarations in the built-in namespace are directly available in any other scope, like system tasks and functions, and can be redefined by user code in any other scope. However, unlike system tasks and functions, the tasks and functions in the built-in namespace may not be redefined by PLI functions.

 

built_in_data_type ::= [ :: ] data_type_identifier                                                                                                         // Not in Annex A

 

built_in_function_call ::= [ :: ] built_in_identifier

 

The scope resolution operator :: with no identifier on the left can be used to unambiguously access names in the built-in namespace. For example:

 

::sys_task();          // unambiguously call the system provided sys_task

 

Unlike system tasks and functions, tasks and functions in the built-in namespace need not be prefixed with a $ to avoid collisions with user-defined identifiers. This mechanism allows functional extensions to the language in a backward compatible manner, without the addition of new keywords or polluting local name spaces.

 

Section 7.12 (new)

LRM-11

Add to new Section 7.12 (Renumber existing 7.12 through 7.15) (change in red):

 

7.12 Static Prefixes

 

Informally, the “longest static prefix” of a select is the longest part of the select for which an analysis tool has known values following elaboration. This concept is used when describing implicit sensitivity lists (see Section 9.2) and when describing error conditions for drivers of logic ports (see Section 5.6). The remainder of this section defines what constitutes the “longest static prefix” of a select.

 

A field select is defined as a hierarchical name where the RHS of the last “.” hierarchy separator identifies a field of a variable whose type is a struct or union declaration. The field select prefix is defined to be the LHS of final “.” hierarchy separator in a field select.

 

An indexing select is a single indexing operation. The indexing select prefix is either an identifier or, in the case of a multidimensional select, another indexing select. Array selects, bit selects, part selects, and indexed part selects are examples of indexing selects.

 

The definition of a static prefix is recursive and is defined as follows:

 

1) an identifier is a static prefix

2) a field select is a static prefix if the field select prefix is a static prefix

3) an indexing select is a static prefix if the indexing select prefix is a static prefix and the select expression is a constant expression.

 

The definition of the longest static prefix is defined as follows:

 

1) an identifier that is not the field select prefix or indexing select prefix of an expression that is a static prefix

2) a field select that is not the field select prefix or indexing select prefix of an expression that is a static prefix

3) an indexing select that is not the field select prefix or indexing select prefix of an expression that is a static prefix.

 

Examples:

 

localparam p = 7;

reg [7:0] m [5:1][5:1];

integer i;

 

m[1][I]       // longest static prefix is m[1]

m[p][1]       // longest static prefix is m[p][1]

m[i][1]       // longest static prefix is m

 

Section 7.17 (new after renumbering above)

LRM-16

Change (change in red):

 

7.17 Set membership

 

SystemVerilog supports integer value sets and set membership operators.

 

The syntax to define a set expression is:

 

inside_expression ::= expression inside range_list_or_array                                                                                                                                       // from Annex A.8.3

 

range_list_or_array ::=

  variable_identifier

| { value_range { , value_range } }

 

value_range ::=

  expression

| [ expression : expression ]

Syntax 7-2—inside expression syntax (excerpt from Annex A)

 

expression is any integral SystemVerilog expression.

 

range_list_or_array is a comma-separated list of integral expressions and ranges. Value ranges are specified in ascending order with a low and high bound, enclosed by square braces [ ], and separated by a colon ( : ), as in [low_bound:high_bound]. Ranges include all of the integer elements between the bounds. If the bound to the left of the colon is greater than the bound to the right the range is empty and contains no values.

 

The inside operator evaluates to true if the expression is contained in the set; otherwise it evaluates to false.

 

For example:

 

                if ( a inside { [16:23], [32:47] } )

 

       if (a inside {b, c})

 

Set values and ranges can be any integral expression. Values can be repeated, so values and value ranges can overlap.