A SystemVerilog description
consists of connected threads of execution or processes. Processes are objects
that can be evaluated, that can have state, and that can respond to changes on
their inputs to produce outputs. Processes are concurrently scheduled elements,
such as initial blocks. Example of processes include, but are not limited to,
primitives, initial, and
always, always_comb, always_latch, and always_ff
procedural blocks, continuous
assignments, asynchronous tasks, and procedural assignment statements.