Section 20.2

LRM-45

Change in Syntax 20-1 (change in red):

local_parameter_declaration ::=

localparam [ signing ] { packed_dimension } [ range ] list_of_param_assignments ;

| localparam data_type list_of_param_assignments ;

parameter_declaration ::=

parameter [ signing ] { packed_dimension } [ range ] list_of_param_assignments

| parameter data_type list_of_param_assignments

| parameter type list_of_type_assignments

specparam_declaration ::=

specparam [ packed_dimension range ] list_of_specparam_assignments ;

LRM-90

Change in Syntax 20-1 (change in red):

constant_declaration ::= const data_type const_assignment ; // from Annex A.2.1.3

LRM-90

Change in Syntax 20-1 (change in red):

const_assignment ::= const_identifier = constant_expression // from Annex A.2.4

param_assignment ::= parameter_identifier = constant_param_expression // from Annex A.2.4

LRM-86

Change in Syntax 20-1 (change in red):

type_assignment ::= type_identifier = data_type

parameter_port_list ::= // from Annex A.1.4

# ( list_of_param_assignments { , parameter_port_declaration } )

| # ( parameter_port_declaration { , parameter_port_declaration } )

parameter_port_declaration ::=

parameter_declaration

| data_type list_of_param_assignments

| type list_of_type_assignments

LRM-86

Changes (change in red):

A module, interface, program, or class or an interface can have parameters, which are set during elaboration and are constant during simulation. They are defined with data types and default values. With SystemVerilog, if no data type is supplied, parameters default to type logic of arbitrary size for Verilog-2001 compatibility and interoperability.

LRM-86

Add at end of section (change in red):

SystemVerilog also adds the ability to omit the parameter keyword in a parameter port list.

class vector #(size = 1);

logic [size-1:0] v;

endclass

typedef vector#(16) word;

interface simple_bus #(AWIDTH = 64, type T = word) (input bit clk) ;

endinterface

LRM-102

Add at end of section (change in red):

In a list of parameters, a parameter can depend on earlier parameters. In the following declaration, the default value of the second parameter depends on the value of the first parameter. The third parameter is a type, and the fourth parameter is a value of that type.

module mc # (int N = 5, M = N*16, type T = int, T x = 0)

( ... );

...

endmodule