A library is a named
collection of cells. A cell is a module, macromodule,
primitive, interface, program, package, or configuration. A configuration is a
specification of which source files bind to each instance in the design.
21.3 Library map files
Verilog 2001 specifies that library declarations, include statements, and config declarations are normally in a mapping file that is
read first by a simulator or other software tool. SystemVerilog
does not require a special library map file. Instead, the mapping information can be specified in the $root top
level.