function_data_type8 ::=
data_type_common_item
integer_vector_type { packed_dimension } [ range
]
| integer_atom_type
| type_declaration_identifier
{ packed_dimension
}
| non_integer_type
| struct [packed ] {{ struct_union_member } } { packed_dimension
}
| union
[ packed ] { { struct_union_member
} } { packed_dimension }
| enum [ integer_type
{ packed_dimension } ]
{ enum_identifier [ = constant_expression ] { , enum_identifier
[ = constant_expression ] } }
| string
| chandle
| void
10.4 Task and function scope and lifetime
In
Verilog-2001, the default lifetime for tasks and functions is static. Automatic
tasks and functions must be explicitly declared, using the automatic keyword.
SystemVerilog
adds an optional qualifier to specify the default lifetime of all tasks and
functions declared within a module, interface or program (see Section 16). The
lifetime qualifier is automatic or static. The default lifetime is static.
program automatic test ;
task foo( int a );
// arguments and variables in foo are automatic
...
endtask
endmodule
Class methods
are by default automatic, regardless of the lifetime attribute of
the scope in which they are declared. Classes are discussed in Section 11.