7.15 Tagged union expressions and member access
expression ::= from
Annex A.8.3
...
| tagged union_expression
tagged_union_expression ::=
tagged member_identifier [ expression ]
Syntax 7-2—Tagged union syntax (excerpt
from Annex A)
A tagged union expression (packed or unpacked) is expressed using
the keyword tagged followed by a tagged union member identifier,
followed by an expression representing the corresponding member value. For void
members the member value expression is omitted.
Example:
typedef union tagged {
void Invalid;
int Valid;
} VInt;
VInt vi1, vi2;
vi1 = tagged
Valid (23+34); // Create Valid int
vi2 = tagged
Invalid; // Create an Invalid
value
In the tagged union expressions below, the expressions in braces
are structure expressions (Section 7.14).
typedef union tagged {
struct {
bit [4:0] reg1, reg2, regd;
} Add;
union tagged
{
bit [9:0] JmpU;
struct {
bit [1:0] cc,
bit [9:0] addr;
} JmpC;
} Jmp;
} Instr;
Instr i1, i2;
// Create an Add
instruction with its 3 register fields
i1 = ( e
? tagged Add { e1, 4, ed }; //
struct members by position
: tagged
Add { reg2:e2, regd:3, reg1:19 }); // by name (order irrelevant)
// Create a Jump
instruction, with ``unconditional'' sub-opcode
i1 = tagged
Jmp (tagged
JmpU 239);
// Create a Jump
instruction, with ``conditional'' sub-opcode
i2 = tagged
Jmp (tagged
JmpC { 2, 83 }); //
inner struct by position
i2 = tagged
Jmp (tagged
JmpC { cc:2, addr:83 }); // by name
The type of a tagged union expression must be known from its
context (e.g., it is used in the RHS of an assignment to a variable whose type
is known, or it is has a cast, or it is used inside another expression from
which its type is known). The expression evaluates to a tagged union value of
that type. The tagged union expression can be completely type-checked
statically: the only member names allowed after the tagged keyword are the
member names for the expression type, and the member expression must have the
corresponding member type.
An uninitialized variable of tagged union
type shall be undefined. This includes the tag bits. A variable of tagged union
type can be initialized with a tagged union expression provided the member
value expression is a legal initializer for the
member type.
Members of tagged unions can be read or assigned using the usual
dot-notation. Such accesses are completely type-checked, i.e., the value read
or assigned must be consistent with the current tag. In general, this may
require a runtime check. An attempt to read or assign a value whose type is
inconsistent with the tag results in a runtime error.
All the following examples are legal only if the instruction
variable instr currently has tag Add:
x = i1.Add.reg1;
i1.Add = {19, 4, 3};
i1.Add.reg2 = 4;
7.18
Conditional operator
conditional_expression ::= (From Annex A.8.3) // from Annex A.8.3
expression1 ? {
attribute_instance }
expression2 : expression3
cond_predicate ? { attribute_instance } expression : expression
cond_predicate
::= // from Annex A.6.6
expression_or_cond pattern { &&
expression_or_cond_pattern }
expression_or_cond_pattern ::=
expression | cond_pattern
cond_pattern ::= expression matches pattern
Syntax 7-5—conditional expression syntax
(excerpt from Annex A)
This section describes the traditional notation where cond_predicate is
just a single expression. SystemVerilog also allows cond_predicate to perform pattern matching, and this
is described in Section 8.4.
As defined in Verilog, if expression1 cond_predicate is
true, the operator returns the expression2
first expression,
if false, it returns expression3 the second expression.
If expression1 cond_predicate evaluates to an ambiguous value (x or z), then
both expression2 the first expression and expression3 the
second expression shall be
evaluated and their results shall be combined, bit by bit.
SystemVerilog
extends the conditional operator to non bit-level types and aggregate
expressions using the following rules:
— If both expression2 the first expression and expression3 the
second expression are bit-level types, or a packed aggregate of bit type,
the operation proceeds as defined.
— If expression2 the first expression or expression3 the
second expression is a bit-level type and the opposing
expression can be implicitly cast to a bitlevel type,
the cast is made and proceeds as defined.
— For all other cases, the type of expression2 the first expression and expression3 the second expression must
be equivalent.
If expression1 cond_predicate evaluates to an ambiguous value, then
both expression2 the first expression and expression3 the second expression shall
be evaluated and their results shall be combined, element-by-element. If the
elements match, the element is returned.
If they do not match, then the default-uninitialized value
for that element’s type shall be returned.