A wildcard import makes
each identifier within the package a candidate for import. Each such identifier
is imported only when it is referenced in the
importing scope it is neither declared nor explicitly imported into the
scope. Similarly, a wildcard import of an identifier is overridden by a
subsequent declaration of the same identifier in the same scope. If the same
identifier is wildcard imported into a scope from two different packages, the
identifier shall be undefined within that scope and result in an error if the
identifier is used.
When an
identifier is referenced within a scope, SystemVerilog follows the Verilog name search rules:
— First, the
nested scope is searched (1364-2001 12.6) (including nested module declarations)
— Next, the
compilation-unit scope is searched (including any symbols made available through package import
declarations)
— Finally, the instance hierarchy is searched (1364-2001
12.5))
This allows the same module name, e.g. and2, to occur in different parts of the
design and represent different modules. Note that an alternative way of
handling this problem is to use configurations.
Nested modules with no ports that are not explicitly instantiated
shall be implicitly instantiated once with an instance name identical to the
module name. Otherwise, if they have ports and are not explicitly instantiated,
they are ignored.
18.7 Extern modules
To support separate compilation, extern declarations of a module
can be used to declare the ports on a module without defining the module itself.
An extern module declaration consists of the keyword extern followed by the module name and the
list of ports for the module. Both list of ports syntax (possibly with
parameters), and original Verilog style port declarations can be used. Note
that the potential existence of defparams precludes
the checking of the port connection information prior to elaboration time even
for list of ports style declarations.
typedef
struct struct
{
bit
isfloat;
union
{ int
i; shortreal
f; } n;
} tagged_st; // named
structure
module
mh1 (input int in1, input
shortreal in2, output
tagged_st out);
...
endmodule
module_instantiation ::= // from Annex
A.4.1.1
module_identifier [ parameter_value_assignment
] module_instance hierarchical_instance { , module_instance hierarchical_instance } ;
module_instance hierarchical_instance ::= name_of_instance ( [ list_of_port_connections ] )
name_of_instance ::= module_instance_identifier instance_identifier { unpacked_dimension }
module_instance ::= name_of_instance
( [ list_of_port_connections ] )
name_of_instance ::= module_instance_identifier
{ range }