endmodule
SystemVerilog adds the ability for local parameters to be declared
in a generate block. Local parameters
can also be declared in a package or in a compilation unit scope. In these contexts, the parameter keyword may be used as a synonym for the localparam keyword.
$ can be assigned to parameters of integer types. A parameter to
which $ is assigned shall only be used wherever $ can be
specified as a literal constant.
parameter r2 = $;
property inq1(r1,r2);
@(posedge clk) a ##[r1:r2] b ##1 c |=>
d;
endproperty
assert inq1(3);
ma #(.p1(3), .p2(int)) u1(i,o);
//redefines p2 to a type of int
endmodule
EDITOR’S NOTE: “endmodule” is
not paired with “module”, above. Is something missing?
Note that function $isunbounded
is
used for checking the validity of the actual
arguments.
EDITOR’S NOTE: The last part of
the previous sentence “...the validity actual arguments” does not make sense.
Should it be “...the validity of the actual arguments”?
interface quiet_time_checker( clk, reset_n, en);
input reset_n;
input clk;
input [1:0] en;
parameter min_quiet = 0;
parameter max_quiet = 0;
interface quiet_time_checker
#(parameter min_quiet = 0, parameter max_quiet = 0)
(input
logic clk, reset_n, [1:0]en);
EDITOR’S NOTE: Is there a reason
the old Verilog-95 style port and parameter declarations were used? If not, it
would be better to use the Verilog-2001 style declarations.
interface width_checker(clk, reset_n, expr);
input clk;
input reset_n;
input expr;
parameter min_cks = 1;
parameter max_cks = 1;
interface width_checker
#(parameter min_cks = 1, parameter max_cks = 1)
(input
logic clk, reset_n, expr);
EDITOR’S NOTE: Is there a reason
the old Verilog-95 style port and parameter declarations were used? If not, it
would be better to use the Verilog-2001 style declarations.