A variable can be static (storage allocated on instantiation
and never de-allocated) or automatic (stack storage allocated on entry to a scope (such as a task,
function or block) and
de-allocated on exit). C has the keywords static and auto.
SystemVerilog follows Verilog in respect of the static default storage class,
with automatic tasks and functions, but allows static to
override a default of automatic for a particular variable in such tasks and
EDITOR’S NOTE: Should the list
of automatic variable items in the first sentence include variables declared
within a for-loop initialization?
SystemVerilog also allows
data to be explicitly declared as static. Data declared to be static
in an automatic task, or function or in a process has a static lifetime and a scope
local to the block. This is like C static data declared within a function.