Section 1
Introduction
to SystemVerilog
This document specifies the Accellera extensions for a
higher level of abstraction for modeling and verification with the Verilog
Hardware Description Language. These additions extend Verilog into the systems
space and the verification space. and was SystemVerilog is
built on top of the work of the IEEE Verilog 2001 committee.
Throughout this document:
“Verilog” or “Verilog-2001” refers to the IEEE Std.
1364-2001 standard for the Verilog Hardware Description Language
“SystemVerilog” refers to the Accellera extensions to
the Verilog-2001 standard.
This document numbers the generations of Verilog as
follows:
“Verilog 1.0”
is the IEEE Std. 1364-1995 Verilog standard, which is also called Verilog-1995
“Verilog 2.0”
is the IEEE Std. 1364-2001 Verilog standard, commonly called Verilog-2001; this
generation of Verilog contains the first significant enhancements to Verilog
since its release to the public in 1990
“SystemVerilog 3.x” is Verilog-2001 plus an extensive set of high-level abstraction
extensions, as defined in this document
SystemVerilog 3.0, approved as an Accellera standard
in June 2002, includes enhancements primarily directed at high-level
architectural modeling
SystemVerilog 3.1, approved as an Accellera standard
in May, 2003, includes enhancements primarily directed at advanced verification
and C language integration
SystemVerilog 3.1a, approved as an Accellera standard in , includes corrections and clarifications to the
SystemVerilog 3.1 manual, as well as some additional enhancements to Verilog
such as VCD and PLI specifications for SystemVerilog constructs.
The Accellera initiative to extend Verilog is an
ongoing effort under the direction of the Accellera HDL+ Technical
Subcommittee. This committee will continue to define additional enhancements to
Verilog beyond SystemVerilog 3.1a.
SystemVerilog is built on top of Verilog 2001.
SystemVerilog improves the productivity, readability, and reusability of
Verilog based code. The language enhancements in SystemVerilog provide more
concise hardware descriptions, while still providing an easy route with
existing tools into current hardware implementation flows. The enhancements also provide extensive support for directed
and constrained-random testbench development, coverage driven verification, and
assertion based verification.
SystemVerilog 3.0 adds
several extended
and new constructs to Verilog-2001. These ,
including:
C data types to provide better encapsulation
and compactness of code
int, typedef, struct, union, enum
Enhancements to
existing Verilog constructs, to provide tighter specifications
Extensions to always blocks to include linting type features
Logic (0, 1, X, Z) and bit (0, 1) data types
Automatic/static specification on a per
variable instance basis
Procedural break, continue, return
Interfaces to encapsulate communication and
facilitate “Communication Oriented” design
Dynamic processes for modeling pipelines
A $root top level hierarchy which can have
global definitions
SystemVerilog 3.1 adds verification
enhancements in the following important areas:
Verification Functionality: Reusable, reactive
testbench data-types and functions.
Built-in types: string, associative array,
and dynamic array
Pass by reference subroutine arguments
Synchronization: Mechanisms for dynamic
process creation, process control, and inter-process communication:
Enhancements to existing Verilog events
Built-in synchronization primitives:
Semaphore, Mailbox
Classes: Object-Oriented mechanism that
provides abstraction, encapsulation, and safe pointer capabilities
Dynamic Memory: Automatic memory management
in a re-entrant environment that frees users from explicit de-allocation
Cycle-Based Functionality: Clocking blocks
and cycle-based attributes that help reduce development, ease maintainability,
and promote reusability:
Cycle-based signal drives and samples
Synchronous samples
Race-free program context
Assertion mechanism for
verifying design intent and functional coverage intent.
Property and sequence declarations
Assertions and Coverage statements with
action blocks
SystemVerilog 3.1a adds several new
constructs and changes:
Definition and support of a compilation unit
Packages containing declarations such as
data, types, classes, tasks and functions
Separate compilation support
A compilation-unit scope visible only within
a compilation unit
Removal of the $root global declaration
space from SystemVerilog 3.1
Extensions to data types for better
encapsulation and compactness of code and for tighter specification
C data types: int,
typedef, struct, union, enum
other data types: bounded queues, logic (0, 1,
X, Z) and bit (0, 1), tagged unions for safety
dynamic data types: string, classes, dynamic
queues, dynamic arrays, associative arrays including automatic memory
management freeing users from de-allocation issues
dynamic casting and bit-stream casting
Automatic/static specification on a per
variable instance basis
Extended operators for consise
description
Wild equality and inequality
built-in methods to extend the language
operator overloading
streaming operators
set membership
Extended procedural statements
pattern matching on selection statements for use
with tagged unions
enhanced loop statements plus the foreach statement
C like jump statements: return, break,
continue
final blocks that executes at the end of
simulation (inverse of initial)
extended event control and sequence events
Enhanced process control
Extensions to always blocks to include synthesis consistent
simulation semantics
Extensions to fork…join to model pipelines and for enhanced process
control
Fine-grain process control
Enhanced tasks and functions
C like void functions
pass by reference
default arguments
pass by name
optional arguments
import/export functions for DPI (Direct Programming
Interface)
Classes: Object-Oriented mechanism that
provides abstraction, encapsulation, and safe pointer capabilities
Automated testbench support with random
constraints
Inter-process communication synchronization
semaphores
mailboxes
event extensions, event variables, and event sequencing
Clarification and extension of the
scheduling semantics
Cycle-Based Functionality: Clocking blocks
and cycle-based attributes that help reduce development, ease maintainability,
and promote reusability:
Cycle-based signal drives and samples
Synchronous samples
Race-free program context
Assertion mechanism for
verifying design intent and functional coverage intent.
Property and sequence declarations
Assertions and Coverage statements with
action blocks
Extended hierarchy support
Packages for declaration encapsulation with
import for controlled access
Compilation-unit scope nested modules and
extern modules for separate compilation support
Extension of port declarations to support
interfaces, events, and variables.
$root to provide unambiguous access using
hierarchical references
Interfaces to encapsulate communication and
facilitate “Communication Oriented” design
Functional coverage
Direct Programming Interface (DPI) for
clean, efficient interoperation with other languages (C provided)
Assertion API
Coverage API
Data Read API
VPI extensions for
SystemVerilog constructs
Concurrent assertion formal semantics