Section 5.3

LRM-223

Changes (change in red and blue):

A static constant declared with the const keyword can only be set to an expression of literals, parameters, local parameters, genvars, enumerated names, a constant function of these, or other constants. The parameters, local parameters or constant functions can have hierarchical names. This is because the static constants declared with the const keyword are calculated after elaboration. An automatic constant declared with the const keyword can be set to any expression that would be legal without the const keyword.

LRM-225

Changes (change in red and blue):

SystemVerilog enhancements to parameter and localparam constant declarations are presented in Section 21. SystemVerilog does not change localparam and specparam constants declarations. A const form of constant differs from a localparam constant in that the localparam must be set during elaboration, whereas a const can be set during simulation, such as in an automatic task.

Section 5.5

LRM-201

Changes (change in red and blue):

SystemVerilog also allows data to be explicitly declared as static. Data declared to be static in an automatic task, or function, block has a static lifetime and a scope local to the block. This is like C static data declared within a function.