A field select is defined
as a hierarchical name where the RHS right-hand-side of the last “.” hierarchy separator identifies a field of a variable
whose type is a struct
or union declaration. The field select prefix is defined to be
the LHS left-hand-side
of final “.”
hierarchy separator in a field select.
m[1][I i]
// longest static prefix is m[1]
Refer to Sections 2.7 and
2.8 for more information on initializing
arrays and structures.
SystemVerilog determines
the context of the braces when used in the context of an assignment. If used in
the context of an assignment to an unpacked array, the braces represent an
unpacked array literal or expression. Outside the context of an assignment on
the right hand side, an explicit cast must be used with the braces to
distinguish it from a concatenation.
Note an
aggregate expression cannot be used as the target of an assignment. The following is considered illegal:
logic [2:0] a [1:0];
logic [2:0] b ,c;
always {b,c} = a; // illegal
assignment the braces are not determined to be an unpacked array expression.
If the type key, default
key, or replication operator is used on an expression with side effects, the
number of times that expression evaluates is
undefined.
A structure expression
(packed or unpacked) can be built from member expressions using braces and commas,
with the members in declaration order. Replicate
operators can be used to set the values for the exact number of members. Each member expression shall be evaluated in
the context of an assignment to the type of the corresponding member in the
structure. It can also be built with the names of the members.
Of If the type key, default key, or replication operator is
used on an expression with side effects, the number of times that expression evaluates
is undefined.
// Create a Jump
instruction, with "unconditional" sub-opcode
i1 = tagged Jmp (tagged tagged
JmpU 239);
// Create a Jump
instruction, with "conditional" sub-opcode
i2 = tagged Jmp (tagged tagged
JmpC { 2, 83 }); // inner struct by position
i2 = tagged Jmp (tagged tagged
JmpC { cc:2, addr:83 }); //
by name
The type of a tagged union
expression must be known from its context (e.g., it is used in the RHS right-hand-side
of an assignment to a variable whose type is known, or it is has a cast, or it
is used inside another expression from which its type is known). The expression
evaluates to a tagged union value of that type. The tagged union expression can
be completely type-checked statically: the only member names allowed after the tagged
keyword are the member names for the
expression type, and the member expression must have the corresponding member
type.
Two functions
cannot have the same arguments and different return types. For example, suppose there is a structure type float:
The overloading
declaration links the + operator to each function prototype according to the
equivalent argument types in the overloaded expression, which normally must
match exactly. The exception is if
the actual argument is an integer integral type and there is only one prototype with a
corresponding integer integral argument, the actual is implicitly cast to
the type in the prototype.
slice_size ::= ps_type_identifier | constant_expression
{
<< 2 { {
<< { 4’b1101 }} }} // generates stream
’b1110
int
a, b, c;
logic [10:0]
up [3:0];
logic [11:1] p1, p2, p3, p4;
bit
[96:1] y = {>>{ a, b, c }}; //
OK: pack a, b, c
int
j = {>>{ a, b, c }}; //
error: j is 32 bits < 96 bits
bit
[99:0] b d = {>>{ a, b, c }}; //
OK: b is padded with 4 bits
{ >> {
a, b, c }} = 23’b1; // error: too
few bits in stream
{ >> {
a, b, c }} = 96’b1; // OK: unpack a
= 0, b = 0, c = 1
{ >> {
a, b, c }} = 100’b1; // OK: unpack
as above (4 bits unread)
{ >> {p1, p2, p3, p4}} = up // OK: unpack p1 = up[3],
p2 = up[2], p3 = up[1], p4 = up[0]
SystemVerilog extends the
conditional operator to non bit-level integral types and aggregate expressions using the
following rules:
— If both first expression
and second expression are bit-level
types, or a packed aggregate of bit
integral type, the operation proceeds as
defined.
— If first expression or
second expression is a bit-level an integral type and
the opposing expression can be implicitly cast to a
bit-level an integral type, the cast is made and proceeds as defined.
The following link is broken (not hyperlinked) even
though it is the correct link.
Annex A.8.3