statement_item ::=
blocking_assignment ;
| nonblocking_assignment ;
| procedural_continuous_assignments ;
| procedural_continuous_assignment ;
| case_statement
| conditional_statement
| inc_or_dec_expression ;
| subroutine_call_statement
| disable_statement
| event_trigger
| loop_statement
| jump_statement
| par_block
| procedural_timing_control_statement
| seq_block
| wait_statement
| procedural_assertion_item
| procedural_assertion_statement
| clocking_drive ;
| randsequence_statement
| scope_randomize
| randcase_statement
| expect_property_statement
blocking_assignment ::=
variable_lvalue = delay_or_event_control expression
| hierarchical_dynamic_array_variable_identifier [ ] = dynamic_array_new
| class_variable_identifier = class_new
| class_variable_identifier . randomize [ ( )
] with constraint_block
| operator_assignment
In Verilog, there are three
types of case statements, introduced by case, casez
and casex. With SystemVerilog, each of these can be qualified
by priority or unique. A priority case shall act on the first match only. A unique
case shall guarantee no check for overlapping case values items, allowing the case
items to be evaluated in parallel. A unique case
shall issue a warning message if more than one case item
matches the case expression. If the case is qualified as priority or unique, the simulator shall issue an error a warning message if an unexpected no case value is
found item
matches. These warnings can be issued at either
compile time or run time, as soon as it is possible to determine the illegal
condition.
loop_statement ::=
forever statement_or_null
| repeat ( expression ) statement_or_null
| while ( expression ) statement_or_null
| for ( for_initialization ; expression ; for_step )
statement_or_null
| do statement_or_null while ( expression ) ;
| foreach ( array_identifier [ [ loop_variables ] ] ) statement
loop_variables ::= [ index_variable_identifier ] { , [ index_ variable_identifier ] }