Section Glossary

LRM-235

From Ralph Duncan (SV-CC)

 

Please find below a plain text (as opposed to rich text) version that one hopes will not look so horribly mangled after its processing by the SV-CC server.

 

With contrition,

Ralph Duncan

Mentor Graphics

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--- Glossary Items

 

canonical

representation          A data representation format established by convention into which and

                        from which translations can be made with specialized representations.

 

context imported task   A DPI imported task declared with the 'context' property that is

                        capable of calling exported tasks or functions and capable of

                        accessing System Verilog objects via VPI or PLI calls.

 

disable protocol        A set of conventions for setting, checking and handling disable status.

 

exported task           A System Verilog task that is declared in an export declaration and

                        can be enabled from an imported task.

 

imported task           A DPI foreign code subprogram that can call exported tasks and can directly

                        or indirectly consume simulation time. 

 

open array              A DPI array formal argument for which the packed or unpacked dimension size

                        (or both) is not specified and for which interface routines describe the size

                        of corresponding actual arguments at runtime.  

 

From Dave Rich (SV-BC)

Aggregate

An aggregate expression, variable or type represents a set or collection of singular values. An aggregate type is any unpacked structure, unpacked union, or unpacked array data type. Aggregates may be copied or compared as a whole, but not typically used in an expression as a whole.

Bit-stream

A bit-stream type or variableis any type that can be represented as a serial stream of bits. To qualify as a bit-stream type, each and every bit of the type must be individually addressable. This means that a bit-stream type can be any type that does not include a handle, chandle, real, shortreal, or event.

Constant

There are two types of constants in SystemVerilog. Parameters and localparam are elaboration constants. Their values are calculated before elaboration is complete. Elaboration constants can be used to set the range of array types. The other form of constant is a runt-time constant. These are variables that can only be set in an initialization expression using the const qualifier.

Dynamic

A dynamic type or variable is one that can be resized or re-allocated at runtime. Dynamic types include those that contain dynamic arrays, associative arrays, queues, or class handles

Integral

An integral expression, variable or type is used to represent integral, or integer value They may also be called vectored values. .Integrals may be signed or unsigned, sliced into smaller integral values, or concatenated into larger values.

Signal

A signal is an informal term, usually meaning either a variable or net. The context where it is used may imply further restrictions on allowed types.

Singular

A singular expression, variable or type represents a single value, symbol, or handle. A singular type is any type except an unpacked structure, unpacked union, or unpacked array data type.