Section E.1

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Some SystemVerilog types are directly compatible with C types; defining a matching C type for them is straightforward. There are, however, SystemVerilog-specific types, namely packed types (arrays, structures, and unions), 2-state or 4-state, which have no natural correspondence in C. DPI does not require any particular representation of such types and does not impose any restrictions on SystemVerilog implementations. This allows implementers implementers to choose the layout and representation of packed types that best suits their simulation performance.

Section E.6.4

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The DPI interface also supports the SystemVerilog and C unsigned integer data types that correspond to the mappings Table E-1 shows for their signed equivalents.

 

Note that input mode arguments of type byte unsigned and shortint unsigned are not equivalent to bit[7:0] or bit[15:0], respectively, since the former are passed as C types unsigned char and unsigned short and the latter are passed as C unsigned int (i.e., svBitVec32).  A similar lack of equivalence applies to passing such parameters by reference for output and inout modes.

Section E.6.6

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For example, if logic logic [2:3][1:3][2:0] b [1:10] [31:0] is used in SystemVerilog, it needs to be defined in C as if it were declared in SystemVerilog in the following normalized form: logic logic [17:0] b [0:9] [0:31].

Section E.9.1.4

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Although the put/get functionality provided for bit bit and logic logic packed arrays is sufficient, yet basic, it requires unnecessary copying of the whole packed array when perhaps only some bits are needed. For the sake of convenience and improved performance, bit selects and limited (up to 32 bits) part selects are also supported, see Annex E.10.3.1 and Annex E.10.3.2.

Section E.11.3

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      Packed arrays (bit bit or logic logic) are accessed via copying to or from the canonical representation.

       

      Scalars (1-bit value of type bit bit or logic logic) are accessed (read or written) directly.

Section E.11.11

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function void myfunc (output logic logic [31:0] r); ...