SystemVerilog 3.1a Face-to-face Meeting 4 March 2004 Attendees: Arif Samad - Synopsys Bassam Tabbara - Novas Brad Pierce - Synopsys Cliff Cummings - Sunburst Design David Smith - Synopsys Dennis Brophy - Model Tech Doug Warmke - Model Tech Faisal Haque - Cisco Systems. Jonathan Bradford - Micronas Ghassan Khoory - Synopsys Jay Lawrence - Cadence Johny Srouji - Intel Kasumi Hamaguchi - Panasonic M. Kaba Mawarabayashi - NEC Mehdi Mohtashemi - Synopsys Neil Korpusik - Sun Oz Levia - Synopsys Peter Flake - Synopsys Surrendra Dudani - Synopsys Takaaki Akashi - Synopsys Vassilios Gerousis - Infineon 1. Review status Covered slides SV-EC: David SV-CC: Ghassan SV-AC: Arif Some of the changes were based on PSL alignment SV-BC: Johny 2. LRM Issues BNF - discussed the good work that has been done by Brad on simplifying and normalizing the BNF. Jay - this is the best the Verilog BNF has ever looked. Dennis - Will be filing some errata on BNF to IEEE 1364 committee. 3. JEITA update Kasumi Hamaguchi Introduction to the JEITA SV activities Organization and Management: Merger of JEDIA and EIAJ Activities: Standardization subcomittee - collaborate with Accellera, IEEE, IEC. SV task group System-C task group Deci-micron design study group - .10 micron and below eD&S fair executive commitee SV Task group activities October 2003 Meetings in Oct, Nov, Feb and March. Reviewing 3.1a Draft4 - feedback by Q4 2004 to Accellera or IEEE WG Participate in balloting Members Cadence, Fujitsu, Renesas, Mengot, Matsushita, Nihon, etc... 4. LRM Issues What are the big issues? Peter: Even with the best will in the world you do not see some of the problems until implemented. Arif: Bulk of issues have been made. Surrendra: A couple of simple assertions issues Cliff: Very pleased with the document. Removed a number of errors. Language is more consistent. We will still find some problems but it is of good quality to pass on. Dennis: I still like VHDL. Implementation helps us to see with greater detail. Ghassan: Difference between 3.0, 3.1, and 3.1a are very evident. Mehdi: We did a lot of ground work from 3.0 and 3.1. For 3.1a it was easier to get the process rolling. As we continue implementation there will still be some refinement. Doug: I am also pleased with 3.1a over 3.1. Glad we took some extra time. We are finding things through implementation, and will find more. Lot of effort to consolidate information so it is easier to understand. I hope more of this continues. We will also continue an approved errata list. This is a good idea. Brad: I actually make a lot of work for other people. It is same thing during implementation. It has helped a lot in the LRM. There will still be more questions. Neil: I think the quality is very high. I am pleased with how much we were able to do in 3.1a. Everything I wanted is there. I am amazed at how much has been put into this effort. I do like the errata list as we move forward. We will find more stuff. Takaaki: We read a draft without any progress information. It is better to not read the drafts. Kasumi: When is a good time to start reviewing 3.1a? Vassilios: Draft 5 is a good point to start. Bassam: The assertion and VPI has made greate stride. I feel confident with the interfaces. Johny: I think it looks good. Some issues from implementation or usage. I feel we are in good ship in language. It was good to have a language owner. Faisal: The assertion part is a big improvement over 3.1. We are receiving some feedback on draft 5. Have we peeked on the responses? Jay: One of my mantras within Cadence has been if you do not get bug reports then you are not getting any usage. This is a good sign. A lot of progress has been made on cleaning up things from 3.1. We did a lot more than just cleaning things up. We have added a lot of new functionality. We could have spent more time on clean-up. Having said that the things that came in were good things. The alignment has made a lot of progress. The work on cover groups and the clean-up is great. There will be comments from us. There will be one or two more. We still have a bunch of concerns on the data type stuff, dynamic allocation of other items besides classes. We will be producing a ballot comment. There will be a different style. We will be bringing up issues with solutions in an attempt to be more constructive. The improvements in randomization are good. More could be done. Completion of the VPI is good. There are still items missing. We will have to either do the work or have the IEEE work on it. A personal perspective on the language, as we have gotten further in implementation. I have spent more time on unification. As talking with classes and looking at implementation it is not clear that unification is a good idead. It may make it easier to comprehend to customers. This is causing us to take a different view of unification. When I talk to users, most do not care. The like the ability to look at sections of the document related to the functionality. Faisal: Are you suggesting breaking up the LRM? Jay: No. It is already partitioned. Once you internalize that there are backward compatability issues, usage issues, etc. it is clear that unification will not happen. Cliff: What does Cadence view about what has not been unified between PSL and SVA? Jay: We think it has gone as far as it can go without making major changes in either language. We believe we can implementation SVA on top of the same infrastructure for PSL and System-C without major problems for users or implementation. Faisal: There are benefits for unification that may make it easire for users. Jay: The sampling of signals in assertions and clocking blocks is one area that the LRM should unify the definition of sampling semantics. Does it make it any easier for the user? Probably not. The way it is defined currently it is clear to the user reading the LRM to see the description on assertions separate from the description for clocking blocks. Vassilios: Note that we have delayed the schedule twice to improve the quality. If there are major issues we will delay it again. My goal is to have a quality document to send to the IEEE. We will continue to do an official errata and send it with the final document. Any issues? Jay: Last year we had a month between the committee recommendation and TCC vote. Is there a process issue here? Vassilios: The time is between the approval of the LRM by the committee and the board approval. David: Stu has raised the concern about his ability to finish the LRM by 15 March. Dennis: There are some schedule issues about having a "town meeting" before the completion of the board approval. Vassilios: March 15 may be delayed by a couple of days. In June we will be transferring this to the IEEE with the errata. So, what is next for Accellera? Options: 1. Provide models to qualify the tools. Extract the examples from the LRM and post on the site. Jay: There are two companies that provide regression suites for SV. Vassilios: Any donations of models would be appreciated. This includes designs and testbenches. Jay: There has been some history in other committees. The government funded some early development that resulted in disagreement about whether they were correct. Compliance can be a problem. Certification programs can result in lots of work and possible problems. Jonathan: Would there be results? Neil: Most of the examples do not have results. David: The goal on extracting the examples is just to have ones that we have run. 2. How to do accelleration of testbench? Vassilios: We had a number of companies that expressed interest in this area. Jay: Bluespec as well. They are concerned about the same synchronization issues. 3. SystemVerilog-AMS Jay: We have spent a lot of time looking at AMS and 2001. SystemVerilog provides some solutions and some problems. We are very interested in working on this as it moves forward. Peter: Has anyone raised the issue of SV and VHDL interoperability? Jay: Tom Fitzpatrick did yesterday. A number of issues were raised. Are we going to define this as a standard or let it involve. Including System-C would be useful. At FTL, you mentioned VHDL Assertion work. Vassilios: There is activity in 1076 on this. We do not want to conflict with them. Dennis: We have offered this and it is up to 1076 to agree. Vassilios: We will post all of the slides on www.eda.org/sv. David: The last question is what the goal of the Takaaki: Where does the review results go to? There are a lot of questions from customers that I would like to pass on to be addressed. Vassilios: These can be handled by Accellera during the errata process. They will then be passed on to the IEEE with the language. Jay: You can provide to both IEEE and Accellera. Takaaki: Why 3.1a instead of 4.2? Vassilios: It was to indicate that the major effort was to complete the language and get robust.