Proposal for IEEE 1666-2010: a container for modules, ports, and channels

Hello all,

in parametrisable and generic models, arrays of sub-modules, ports,
and channels are often needed and widely used. Unfortunately, this
usually requires the use of pointers and dynamic allocation of the array
elements in a loop, since e.g. modules are rarely default-constructible.

  Frequent questions in public fora and teaching shows, that this causes
troubles especially for inexperienced SystemC/C++ users. To reduce this
limitation of SystemC's expressiveness and ease-of-use, we would like to
propose a container class (working title sc_core::sc_vector), that can
cover the most frequent use cases out-of-the-box and is extensible for
more complex scenarios:

// construct vector with 42 modules
// named "mod_vec_0", "mod_vec_1"...
sc_vector< my_module > mod_vec( "mod_vec", 42 );

// std::vector-like interface
mod_vec.size(), mod_vec.begin(), mod_vec[i].name()

  We've sent in a more detailed proposal, including additional examples
and an initial wording for a potential inclusion in the standard, which
will be added to the document repository at eda.org/systemc, soon. We
can provide a corresponding proof-of-concept implementation upon request.

  An earlier version of this implementation has already been proposed to
the OSCI LWG earlier this year. There has not yet been any decision
inside OSCI, but some positive feedback has been given by individual LWG
members. Since the call for proposed enhancements of IEEE 1666-2005
ends March 10, we wanted to bring this to the P1666 WG in time, though.

Looking forward to any comments, opinions, and criticism ... ;-)

Best regards,
Philipp

-- 
Philipp A. Hartmann
Hardware/Software Design Methodology Group
OFFIS
R&D Division Transportation | FuE-Bereich Verkehr
Escherweg 2 · 26121 Oldenburg · Germany
Phone/Fax: +49-441-9722-420/282 · PGP: 0x9161A5C0 · http://www.offis.de/
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