RE: JEITA's comments and requests for SystemC and TLM-2.0

Bishnupriya,

I had not read the process control spec recently. Of course, multiple
reset signals can be included in the review.

John A

From:
Bishnupriya Bhattacharya <bpriya@cadence.com>
To:
"john.aynsley@doulos.com" <john.aynsley@doulos.com>,
"hiroshi3.imai@toshiba.co.jp" <hiroshi3.imai@toshiba.co.jp>
Cc:
"owner-systemc-p1666-technical@eda.org"
<owner-systemc-p1666-technical@eda.org>, "systemc-p1666-technical@eda.org"
<systemc-p1666-technical@eda.org>
Date:
29/03/2010 18:04
Subject:
RE: JEITA's comments and requests for SystemC and TLM-2.0

John,
 
About issue 1 (# reset_signal_is for an SC_THREAD), the latest revision of
the Cadence process control spec submitted to the LWG on 8th May, 2009,
supports multiple reset_signal_is() specification for a single thread
(Section 2.8.3).
 
I understand the process control extensions are the next enhancement on
your plate to review - are you looking at this latest version of the spec?
 
Thanks,
-Bishnupriya

From: owner-systemc-p1666-technical@eda.org [
mailto:owner-systemc-p1666-technical@eda.org] On Behalf Of
john.aynsley@doulos.com
Sent: Monday, March 29, 2010 7:30 PM
To: hiroshi3.imai@toshiba.co.jp
Cc: owner-systemc-p1666-technical@eda.org; systemc-p1666-technical@eda.org
Subject: Re: JEITA's comments and requests for SystemC and TLM-2.0

Hiroshi-san,

Some remarks on the JEITA comments and requests:

SystemC
1. # of reset_signal_is for an SC_THREAD

        Answer: The SystemC LWG agreed some time ago to explicitly
restrict the number of occurrences of reset_signal_is to 1-per-thread. Do
you intend to raise an enhancement request for more than one reset signal
per thread?

TLM-2.0
1. Insufficient explanation of hop

        Answer: The LRM will say "The entire path between an initiator
and a target consists of a number of hops, each hop connecting two
adjacent components. A hop consists of one initiator socket bound to one
target socket. The number of hops from initiator to target is one less
than the number of interconnect components on that path. When using the
generic payload, the forward and backward paths should each pass through
the same set of components and sockets in opposing directions."
        Is that clear?
        We will add cross-references to the TLM-2 glossary entries.

2. Insufficient explanation of ignorable phase.

        Answer: There is an entire clause (ex. 8.2.5) dedicated to
ignorable phases, complete with examples. I would welcome your input on
how this could be improved.

10. In "attribute", "artefacts" should be "artifacts".

        Answer: "artefact" and "artifact" are variant spellings of the
same word. "artifact" is said to be British spelling, though as a native
British-speaker, I would not notice or care :-)

John A

From:
Hiroshi Imai <hiroshi3.imai@toshiba.co.jp>
To:
systemc-p1666-technical@eda.org
Date:
03/03/2010 04:18
Subject:
JEITA's comments and requests for SystemC and TLM-2.0
Sent by:
owner-systemc-p1666-technical@eda.org

Hello, all,

I send JEITA's comments and requests for SystemC and TLM2.0 in the
EXCEL file attached to this email. It includes requests, comments, and
suggestions.

Best regards,
Hiroshi Imai, chair of JEITA SystemC WG$B:#0f9@;K(B
($B3t(B)$BEl<G(B $B%;%_%3%s%@%/%?!<<R(B
$B%7%9%F%`(BLSI$B@_7W5;=QIt(B
$B@_7W%a%=%I%m%8!<5;=Q3+H/C4Ev(B
mailto:hiroshi3.imai@toshiba.co.jp
TEL:044-548-2346

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