Re: New draft LRM and progress

Some more minor comments:

Section 9.5.7
What is the reason for

"The value of the relation &V[i] + j == &V[i + j] is undefined for all vectors v and for all indices i
and j."

Standard (STL) vectors are guaranteed to be laid out contiguously in memory such that you can just take
the address of the first element and access the contents as though they were a standard C array.

p423
"Class sc_vector_assembly shall be copyable"
I don't have the C++ standard to hand - but does copyable always also mean "assignable"?

18.3.4

The default name for tlm_fifo is sc_gen_unique_name("fifo"). That is the same as
for sc_fifo. So an sc_fifo object and a tlm_fifo object in the same scope would have
duplicate hierarchical names.

Alan

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-----owner-systemc-p1666-technical@eda.org wrote: -----
To: systemc-p1666-technical@eda.org
From: john.aynsley@doulos.com
Sent by: owner-systemc-p1666-technical@eda.org
Date: 19/11/2010 10:23
Subject: New draft LRM and progress
Folks,
I have uploaded a new draft LRM including
sc_vector and sc_writer_policy.
We are now working on just 3 enhancements
plus any other minor issues or corrections, aiming for completion by the
end of November:
* Adding sc_pause and sc_get_status
* Making request_update thread safe
* Naming sc_events
Please keep up the energy levels so
we can complete each of these by end Nov.
Thanks!
John A
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