RE: [tlmwg] Revisit of the TLM2.0 phases rules

Yossi,

  This is not about in-order or out-of-order responses. It is about interrupibility of requests and responses. A
bus that has separate physical wires for read/write address or read/write response is usually interruptible in
this way. Vast numbers of bus protocol standards share the same wires for read/write address and
read/write response. A huge number even share the same wires for read/write data! Where wires are
shared interruption/interleaving is rarely possible.

  Obviously you can use the BP to approximate AXI. Obviously it won't be as good as using a slightly
modified protocol allowing overlapping RD/WR requests and responses, and possibly adding write data
bus phases. The pertinent questions are "how close can you get using the BP and is it really so bad
as to justify losing the BP-compatibility?" The answers will depend on what your component
model is for..................................... (truncated)

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