This is a summary of the reflector discussion that was started with the
email titled:  Request for Input.  A link to it is here:
   http://www.eda.org/vhdl-200x/hm/1091.html
   
In this email Jim asks the study group to further elaborate
on the purpose to the par and specifically:
    What is intended by Verification enhancements?
     1) Create an API/interface/package that allows interfacing
        VHDL to SystemC and/or SystemVerilog/UVM 
        vs
     2) It could also mean we implement full OO and UVM-like
        stuff in VHDL. 


Ben Cohen:  
  #1

Hans:  
  #1 waste of time since vendors already provide vendor specific solution.
  Keep VHDL oriented toward the stringent military/safety critical market.
  Add OO similar to Ada.
  >> Paul Colin Gloster agree
  >> John Bromley - disagree

Ben Cohen:
  VHDL lacking in 
    Data structures (Dynamic arrays, associative arrays, )
    Constrained Random
    Functional Coverage
    System functions
    classes
    interfaces

Rob Anderson
  Need OO in both data objects as well as components, 
  otherwise need to use C++

Daniel Kho
  Make VHDL easier to use, such as simplifying type conversions, 
  and friendlier packages

Sundeep Kumar
  Mailboxes, Semaphores, Fork-Join, [Assertions]

Jonathan Ross
  Ability to capture transactional level timing constraints 
  Abstractions for representing one or more flip-flop stages
  >> Daniel Kho and Sundeep Kumar agree

John Bromley:
  Make easy to use "great slabs" of C++ in a testbench
  Make easy to use script languages (TCL, Python, Ruby)
  Allow use of script language from within VHDL code to do  
    string and file manipulation
  Robust, standardized interfaces to other stuff (XML/IP-XACT)
  low-power a-la UPF and successor to std_logic_1164
  >> Martin Thompson agree with 1st 3 points
  >> Hans agrees with point 1 & suggests that it would allow
     someone to bolt on a constraint solver, ...

Peter Flake
  Adding direct C interface results in easier to inter-operate 
  with other languages such as SystemC and SystemVerilog.
  Note this is very similar to John Bromley's point 1.
  >> Tony Kirke agrees
  
  PSL should be considered to be the assertion language 
  'e' could be considered to be the randomization capability
  >> Evan Lavelle agrees
  
David Bishop
  Bug fixes + updates to fixed/float packages
  
Lance Thompson
  bug fixes, 
  designer productivity improvements, 
  hardware verification language interface standardization.  

Charles Gardiner
  Desired scope of enhancements to future versions of VHDL standard:
  ++ Native language support for transaction level modelling
  ++ Native language support for randomised verification, UVM etc.
  ++ Native language support for IP encryption (P1735?)
  ++ Re-evaluation of interface to other languages, particularily SystemC and SV
  ++ Interchange format for simulation output (waveform dumps, traces etc.)
  ++ Tighter involvement with VHDL-AMS for mixed-signal system modelling
  +  Improvements to TextIo
  
Ernst Christen
  I have a minor concern about the scope and purpose described in the PAR.
  Both are specific to the planned revision. 
  The problem I can see is that recent rule changes at IEEE require 
  both scope and purpose to be included verbatim in the LRM, with no 
  additional text. The implication is that the purpose and scope of the 
  1076-201x standard would then be that of the revision, not of the 
  language as a whole.
  
================================================
The following items are discussion threads that occurred earlier in 2010
  Coordinate with 1076.1 regarding vector/matrix operations and 
  possible generalizations. 
    Reflector thread:  http://www.eda.org/vhdl-200x/hm/1054.html
                       http://www.eda.org/vhdl-200x/hm/1086.html

  Implicit to_integer conversions
    Reflector thread:  http://www.eda.org/vhdl-200x/hm/1051.html
    
  Extending type integer to have more than 32 bits
    http://www.eda.org/vhdl-200x/hm/1023.html
    http://www.eda.org/vhdl-200x/hm/1032.html
    http://www.eda.org/vhdl-200x/hm/1034.html
    
  From Matthias Wachter:
     http://www.eda.org/vhdl-200x/hm/1037.html  -- see quoted email at bottom too
     1) Item set operation "in"
       if X in 0 to 5 then
       vs:
       if X >= 0 and X <= 5 then
       
     6) Is a tool feature, so I am leaving it off.
     
     Other items based on Peter Ashenden's follow-up appear to be implemented
        
  String literal issues in fixed/float packages:
    http://www.eda.org/vhdl-200x/hm/1070.html