Minutes of the Committee call - 1 July 2002


Subject: Minutes of the Committee call - 1 July 2002
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Jul 08 2002 - 11:22:53 PDT


Attendees - Jon (Cadence), Peter, Don (Antrim), Sri, Graham (Motorola)
Date: 1st July, 4:30pm US PST (2nd July 9:00am Adelaide)

Next Meeting: Scheduled for 8th July, 4:30pm US PST (9th July 9:00am Adelaide)

* There was a general discussion as to how we are going to address the next version

* It was agreed that it is very important to release the next version 2.1 with the changes that are currently in hand. It is been about 2.5 years since the LRM 2.0 version was released, and it is critical to do another with the current agreed upon set of changes.

* With regards to the changes for 2.1 version, a few changes have already been proposed and discussed. A few more would be identified to be worked upon the next couple of months. September first week was agreed by all present as the deadline to close all relavent issues that need to go in for LRM 2.1

* For the next revision, it was agreed that the changes since not very huge would be directly changed by the author in to the relavent section of the LRM document in frame format. All these changes would be collated the version sent for review and vote. The frame format available runs is fram6.0 compatible.

* There was some concern with regards to the changes that go across the analog boundary. Ex. compatibility with Verilog 2001, System Verilog etc. Sri made a point that it would be difficult to address these issues unless there is the participation of the relavent committee members so that whats being proposed in meaningful and acceptable.
Question: Should we do the changes for these cases which would make analog more correct without worrying or considering the other side of the fence?

* Sri to send a list of issues that could possibly be taken up in the next 2 months that would go in for 2.1 which would be discussed in the next call.

List of issues that can potentially be addressed in the next couple of months. All the identified issues are fairly minor. More details on these issues could be found in the attached pdf and excel spreadsheet. The spreadsheet specifies the issues as a proritized list of issues, and the pdf document mentions the current status of those.

I have identified the following as the initial list. There are a few more minor ones that I have not picked currently which we can pick it up once we have closed the ones mentioned if we have the time before first week of september.

If anybody else feel that they can contribute to this please do let me know. There pdf and spreadsheet (which has more details) have all the issues listed.

Index Issue Action
 8 1364 sync-up with $random. Martin
11 Issue with genvar. Sync with digital Std Martin
14 Ambiguities with current if-else-if syntax/semantics Sri
16 Initial Value of wreal set to 0.0 if not defined Jon
18 Diagram to reflect example on Section 8.6 Jon
                   regarding bi-dir model
20 Driver Type function. Kevin
24 LRM cleanup typos Sri
25 LRM cleanup - refers to derived disc without Sri
                   BNF support for the syntax
26 Tri & Wire as alias to be specified Jon
27 Syntax inconsistencies between chapter and BNF. Jon
                   6-3, 6-4, 6-5 should reflect BNF
48 `include to support both <> and "" Kevin
50 Specification of roots for Zi Filter in terms of Z^-1 Peter
53 Rules for vector vs scalar connection if the entity Peter
                   is reg rather than a wire type
60 Values for constants file for charge, boltzmann Sri
                   etc should reflect std definitions
63 Updating Annex-C with boundstep change Sri

The following are the ones that would be good if we can make any progress (irrespective of whether it goes in to LRM 2.1 or not)

1 Real values ports vs real nets in sync with System Verilog language
                  definition.
6 Concurrency Problem. LRM does not clearly define MS synchronization
                   mechanism for AMS
7 LRM does not clearly illustrate the MS simulation cycle. IC analysis
                  method is non existent in the current LRM for AMS.
                  The general consensus on this one seems that we should adapt what
                  VHDL-AMS has done
9 Truncating vs Rounding mechanism for converting from analog to digital
                  times
58 Current LRM makes it illegal to have incompatible continous disciplines
                  on the same net. Some of the vendors feel that this will be an useful
                  feature to support and allows user complete control.


v.pdf



This archive was generated by hypermail 2b28 : Mon Jul 08 2002 - 11:25:44 PDT