Re: VAMS-CM: new LRM draft, DAC meeting

Kevin Cameron wrote:
>
> I'd rather extend the [macro]module syntax/semantics to support what you
> need than add a whole new construct, e.g. add inheritance to [macro]modules
> so that you don't have to redefine stuff:
>
> module mos (...)
> ...
> endmodule
> macromodule my_mos interface mos; // inherit port and parameters etc. from mos
> ...
> mos #(...) (.*);
> endmodule
>
> I suggest "interface" rather than "extends" (or ":") since you don't want to
> inherit the internal structure and processes (and "interface" is already a
> keyword).

(Interface is a keyword in SV3.0 and later, but not in 1364-2001 nor AMS.)

It's an interesting suggestion. A few points:

1) We don't want to inherit parameters from mos, only the ports
(and output variables).

2) It's not clear to me that this is really what the SV interface
is meant to do.

3) It seems that the interface, that is, the base module definition,
would need to preceed the macromodule my_mos; but in typical use,
I doubt the bsim6 module definition would even be in the same file
as the paramsets/macromodules.

-Geoffrey
Received on Thu Jun 17 11:08:37 2004