Verilog-AMS Issues ---------------------------------------------------------------------------- # priority Subject agree/disagree with proposal 1 20 Truncating vs Rounding when converting Analog to Digital times. agree 2 2 Driver-receiver Segregation agree as an addition to LRM 3 1 A/D Convertor placement " 4 10 Driver Type Function agree 5 51 A/D Synchronization disagree 6 33 External Module Definitions disagree 7 15 Back-Annotation agree - needs more work 10 52 Issues on discipline and Nature compatibility disagree 11 28 Issues on if-elseif disagree 12 53 Issues with regards to example on Section 3.8 disagree 13 29 NaN & 'X' agree 14 34 Discipline Compatibility disagree 15 54 `include disagree 16 19 Mixed signal initialization (digital) disagree - needs more work 17 85 Filters for foreign languages disagree 18 86 Light Weight Conversion agree 19 87 Representation Stops disagree I agree with the fact that the 801- issues need (in some cases) much more work - there are no proposals here: 801 30 1.2 Mixed-signal language features 802 35 3.3 Genvars 803 84 3.4.3.{2,3} Empty disciplines; undeclared nets 804 56 3.4.5 Ground declaration 805 24 3.5 Real net declarations 806 57 3.6 Default discipline 807 58 4.4.1 Restrictions on analog operators 808 59 4.4.7 Absolute delay operator 809 60 4.5 Analysis dependent functions 810 61 6.7 Events 811 62 6.7.4 Global events 812 36 7.1.1 Top-level modules 813 63 7.3 Ports xxx 814 7.3.3 Real valued ports same as 805 815 64 8.2.{1,2} Domains. Contexts 816 65 8.3 Behavioral Interaction 817 5 8.3.1 Accessing discrete nets and variables.. 818 6 8.3.6 Concurrency 819 3 8.4 Discipline Resolution 820 66 8.4.3 Connection of continuous-time disciplines 821 7 8.{5-8} Connect Modules 822 8 8.10 Driver Access and net resolution 823 9 8.11 Supplementary driver access functions 824 83 9.2 Mixed-signal simulation cycle 825 17 10 System tasks and functions 826 81 11 Compiler directives 827 82 D Standard definitions xxx 828 E SPICE compatibility - same as below (937) 829 4 F Discipline resolution methods 901 67 Section 3.2.1? - Coercion of strings to real - no proposal allowed but not defined 902 68 Section 3.2.2 (When to do range checks?) - agree 903 69 Section 3.4.2 Connections to port - no proposal expressions (whats a driver?) 904 70 Section 3.4.2 (OOMR disciplines on behavioral nets) - agree 905 71 Section 3.4.3.2 (neutral disciplines) - disagree 906 37 Section 3.4.3.3 .... - LRM cleanup issue: TRI and WIRE are aliases 907 72 Section 3.5 - PCR 328294 Initial - agree value of wreal nets not defined 908 73 Section 3.5 and 7.7.3 - Real value port examples have - agree errors: 909 18 Section 3.6 (default_discipline clarifications) - agree 910 74 Section 3.6 (default_discipline only for digital?) - agree 911 38 Section 3.7 (Discipline presendence issues) - agree 912 39 Section 3.7 - disiplines rules of branches - agree 913 40 Section 3.9 branches - clarifications - disagree 914 25 Section 4.5.1 and 6.7.4 - Initial Conditions - disagree 915 26 Section 5.1.6 (Implicit Switch Branches?) - agree 916 41 Section 5.3.2 (Indirect assignments in conditionals) - agree 917 42 Syntax 6-1 and BNF - agree 918 43 Syntax 6-3, Syntax 6-4, Syntax 6-5 and BNF - agree 919 44 Section 6.4 (Switch branches illegal in BNF) - agree 920 45 Section 7.2 and 1364 - defparam vs. instantiation precedence - agree 921 46 Section 8.2.4 : Compatible disciplines - agree 922 14 Section 8.3.6.4 and 8.3.1 : Clarification on X and Z . - agree 923 31 Section 8.4.4.1 and Annex F - Discipline Resolution: No clear definition on how to deal with "leaf 924 32 Section 8.4 and Annex F - Discipline Resolution: No clear definition on how to deal with out of 925 11 Section 8.6 (bi-dir issues) - agree 926 12 Section 8.10.5 - net_resolution function: No one - agree liked this so if we are going to change it lets do 927 13 Section 8.11 (Supplementary drivers and delays) - disagree 928 76 Section 9 : Which solver starts first? - disagree 929 75 Section 9 Initialization method - Different from VHDL - agree 930 77 Section 10.2 1364 sync-up: Random function for analog - agree not clearly defined but in 1364 it is as the 931 78 Section 12.5.2 (VPI Issue) - agree 932 47 Annex A: BNF clarification - agree to allow 933 48 Annex B - flow and potential, should these be - agree global keywords? 934 49 Annex C changes that were missed: - disagree 935 50 Annex D -Discipline and Constants file corrections: - disagree 936 21 Annex D: -upcase issues with disciplines.vams file - agree 937 22 Annex E. - disagree 938 79 Annex E2: Case sensitive SPICE simulators - disagree 939 80 Annex E.3 - Disciplines of analog primitives: - disagree How to set and defaults. 940 27 LRM Cleanup:(Typos) - agree 941 16 Global Issues: Support for global design variables - agree (accessible throughout hierarchy)