SPICE MODEL CARDS IN VERILOG-A
                                                 S. Peter Liebmann

The purpose of this note is to show how a compact model device in Verilog-a can be 
instantiated in a manner which mimics SPICE.

In SPICE one has a device which refers to a model card which, in turn, refers to 
a built in SPICE model.  For example, a mosfet can be written as:

M1 Drain Gate Source Bulk model_1 l=1u w=10u ...

.model model_l nmos level=... p1= ... p2=...


M1 is the instance which refers to model_l.  The parameters following 'model_l'
are instance parameters (usually geometry parameters) which interact with the 
parameters on the .model card.  Each parameter set is on a unique model card.
It is important to note that the instant parameters cannot change the model parameters.

One can mimic this SPICE behavior with standard Verilog-a by defining a unique module 
for each set of model parameters which, in turn, refers to a particular model.  
The only difference is that this module will contain the instance parameters as well 
as the model parameters.  However, one can write the module such that the instantiation 
does not affect the model parameters (like in SPICE) and a simulator may distinguish 
between model and instance parameters (for more efficient code).

The instantiation of the module will be:

model_1 #(.l(1u), .w(10u),...) M1 (Drain, Gate, Source, Bulk);

module model_1 (d,g,s,b);
inout d,g,s,b;
electrical d,g,s,b;
parameter real l=1u, w=1u ...                // NOTE: only instance parameters here

    Compact_model #(.l(l), .w(w), ... .p1(...), .p2(...) ...) I1 (d,g,s,b);

endmodule

The module will have the following properties:
1. Only instance parameters are on the parameter list.
2. 'Compact_model' is the name of the module containing the Verilog-a description.
3. The instance parameters will be part of the Compact_model instantiation parameter 
   list as well as the model parameters.
4. There is a 1-1 map between the SPICE description and the Verilog_a description.
5. One can easily distinguish between instance and model parameters (no new syntax 
   is needed for this).
6. This has the standard Verilog flexibility for parameters (e.g. parameters may 
   contain expressions, ...) leading to most modified SPICE's features.