VAMS-CM subcommittee meeting, August 10
attendees:
Srikanth Chandrasekaran, Freescale
Geoffrey Coram, Analog Devices
Jim Barby, U Waterloo
Colin McAndrew, Freescale
Laurent Lemaitre, Freescale
Marek Mierzwinski, Tiburon

No one had any further comments; the LRM draft "g"
is fine except for the table model details mentioned
in the AMS meeting.

Colin noted that ADMS and probably other Verilog-A
compilers will continue to use attributes to tag
instance and model parameters to fit the Spice
netlist format; it will be a while before netlisters
generate Verilog-style netlists with paramsets.

If there are any other typos found in draft "g"
please be sure to submit them ASAP.  I will be
sending the LRM to Sri on Thursday afternoon
(Eastern time -- probably around noon Pacific).
Sri asked for the frame source and two PDF
versions, one with and one without change bars.
The version will be "2.2" (no draft letter) and
the date will be "September 2004".

Thank you all for your contributions.