V-AMS Compact Modeling Extensions subcommittee
Minutes of November 18, 2003

Attendees:
Geoffrey Coram, Analog Devices
Ilya Yusim, Cadence
John Moore, Agilent
Colin McAndrew, Motorola
David Zweidinger, Texas Instruments
Marek Mierzwinski, Tiburon
Boris Troyanovsky, Tiburon
Patrick O'Halloran, Tiburon
Peter Liebmann, Xpedion
Jim Barby, U Waterloo
Al Davis, Kettering U

1) Approval of previous minutes (Oct 21).

2) Some people have had trouble compiling ADMS.
The link, again, is http://sourceforge.net/projects/mot-adms

3) Paramsets

Jim was concerned about instantiating modules vs paramsets,
but we feel that the syntax in a Spice-like netlist (for a
simulator that accepts Verilog-A models) will look very much
like a traditional Spice netlist.  One question is whether
a Verilog-A module will be able to use the traditional letters
for the various device types (M for MOS, Q for BJT, etc.) or
if they will all need to use X for some kind of subcircuit.

Al suggested an alternate grouping of parameters, but it
was pointed out that his proposal ends up with an
inflexible partition of model/instance/"common" parameters
that is unsuitable for eg mismatch, where the user has
a different idea about partitioning than the model writer.

Jim noted that binning could be done in conditional branching,
since the paramset proposal allows if() inside a paramset.
However, we feel that we still need the simulator to do
automatic binning in order to quickly convert the huge
number of existing model cards.

Ilya asked a good question: can you define output or operating
point parameters (Sec 1.4 of the main proposal) for paramsets?
Can you hide any of the underlying module's output parameters?
What if you want the paramset to define a new output parameter
that is a function of the module's output parameters?

Cadence has had some user confusion with "in-line subcircuits":
obviously, a traditional Spice subcircuit (say, for a MOS with
extra effects) does not know what "GDS" is, but the user
expects the in-line subckt to know, because it looks like an
instance.

4) Inheritance

Al is interested in something he calls inheritance, which looks
very much like C++ class inheritance.  Eg, you could define a
low-level MOS model with very few parameters, and then more
advanced models would inherit from this base class and add
complexity.  Al has promised us a nice written example.

Bell Labs had the "Asim" series of MOS models, and the users
were able to switch between them on a per-instance basis to
model important transistors with more complicated models;
the simulator would also automatically switch them around
as a sort of homotopy method for DC convergence.

Several attendees were concerned about the level of complications
this would add to the language, and whether this would have
sufficient payback.  There was a feeling that this goes beyond
the mandate of this committee to propose "basic" extensions
to enable device modeling.  We will wait to see Al's example
and try to understand the payback.