main_axiome ::= des_unit
des_unit ::= module_declaration | udp_declaration | discipline_declaration | nature_declaration | connectmodule_declaration | connect_specification
module_declaration ::= module_keyword IDENTIFIER [ list_of_ports ] ';' { module_item } 'endmodule'
module_keyword ::= 'module' | 'macromodule'
list_of_ports ::= '(' port { ',' port } ')'
port ::= [ port_expression ] | '.' IDENTIFIER '(' [ port_expression ] ')'
port_expression ::= port_reference | '{' port_reference { ',' port_reference } '}'
port_reference ::= identifier [ port_reference_end ]
port_reference_end ::= '[' constant_expression port_reference_end_end
port_reference_end_end ::= ']' | ':' constant_expression ']'
module_item ::= module_item_declaration | parameter_override | continuous_assign | gate_instantiation | module_or_udp_instantiation_or_net_discipline_declaration | specify_block | initial_construct | always_construct | something_beginning_by_analog
something_beginning_by_analog ::= 'analog' analog_block | analog_function_declaration
module_item_declaration ::= parameter_declaration | input_declaration | output_declaration | inout_declaration | net_declaration | reg_declaration | integer_declaration | real_declaration | time_declaration | realtime_declaration | event_declaration | task_declaration | function_declaration | ground_declaration | genvar_declaration | branch_declaration
parameter_override ::= 'defparam' list_of_def_param_assignments ';'
nature_declaration ::= 'nature' nature_name [ nature_descriptions ] 'endnature'
nature_name ::= IDENTIFIER [ ':' parent_identifier ]
parent_identifier ::= IDENTIFIER [ '.' pot_or_flow ]
nature_descriptions ::= nature_description { nature_description }
nature_description ::= 'abstol' '=' constant_expression ';' | 'access' '=' IDENTIFIER ';' | 'units' '=' STRING ';' | 'idt_nature' '=' IDENTIFIER ';' | 'ddt_nature' '=' IDENTIFIER ';' | IDENTIFIER '=' constant_expression ';'
nature_attribute ::= 'abstol' | 'access' | 'ddt_nature' | 'idt_nature' | 'units' | IDENTIFIER
discipline_declaration ::= 'discipline' IDENTIFIER [ discipline_descriptions ] 'enddiscipline'
discipline_descriptions ::= discipline_description { discipline_description }
discipline_description ::= net_binding_or_attr_override | domain_binding
net_binding_or_attr_override ::= pot_or_flow nature_binding | attr_override
nature_binding ::= IDENTIFIER ';'
attr_override ::= '.' nature_description
pot_or_flow ::= 'potential' | 'flow'
domain_binding ::= 'domain' 'discrete' | 'continuous' ';'
parameter_declaration ::= 'parameter' [ opt_type ] list_of_param_assignments ';'
opt_type ::= 'real' | 'integer'
list_of_param_assignments ::= declarator_init { ',' declarator_init }
list_of_def_param_assignments ::= def_param_assignment { ',' def_param_assignment }
declarator_init ::= IDENTIFIER '=' constant_expression { opt_value_range } | range '=' constant_som_concatenation { opt_value_range }
opt_value_range ::= 'from' value_range_specifier | 'exclude' constant_expression
value_range_specifier ::= start_paren constant_expression ':' constant_expression end_paren
start_paren ::= '(' | '['
end_paren ::= ')' | ']'
def_param_assignment ::= identifier '=' constant_expression
input_declaration ::= 'input' [ range ] list_of_port_identifiers ';'
output_declaration ::= 'output' [ range ] list_of_port_identifiers ';'
inout_declaration ::= 'inout' [ range ] list_of_port_identifiers ';'
list_of_port_identifiers ::= IDENTIFIER { ',' IDENTIFIER }
reg_declaration ::= 'reg' [ range ] list_of_register_identifiers ';'
time_declaration ::= 'time' list_of_variable_identifiers ';'
integer_declaration ::= 'integer' list_of_variable_identifiers ';'
list_of_variable_identifiers ::= variable_name { ',' variable_name }
variable_name ::= IDENTIFIER [ range ]
real_declaration ::= 'real' list_of_variable_identifiers ';'
realtime_declaration ::= 'realtime' list_of_real_identifiers ';'
event_declaration ::= 'event' list_of_event_identifiers ';'
list_of_real_identifiers ::= IDENTIFIER { ',' IDENTIFIER }
list_of_event_identifiers ::= IDENTIFIER { ',' IDENTIFIER }
list_of_register_identifiers ::= register_name { ',' register_name }
register_name ::= IDENTIFIER [ range ]
range ::= '[' constant_expression ':' constant_expression ']'
ground_declaration ::= 'ground' [ range ] list_of_grounds ';'
list_of_grounds ::= IDENTIFIER [ range ] { ',' IDENTIFIER [ range ] }
list_of_nets ::= IDENTIFIER [ range ] { ',' IDENTIFIER [ range ] }
branch_declaration ::= 'branch' list_of_branches ';'
list_of_branches ::= terminals list_of_branch_identifiers
terminals ::= '(' net_or_port_scalar_expression [ ',' net_or_port_scalar_expression ] ')'
list_of_branch_identifiers ::= IDENTIFIER [ range ] { ',' IDENTIFIER [ range ] }
genvar_declaration ::= 'genvar' list_of_genvar_identifiers ';'
list_of_genvar_identifiers ::= IDENTIFIER { ',' IDENTIFIER }
analog_function_declaration ::= 'function' [ type ] identifier ';' function_item_declaration { function_item_declaration } ad_statement 'endfunction'
type ::= 'real' | 'integer'
net_declaration ::= net_type [ 'vectored' | 'scalared' ] [ drive_strgth ] [ range ] [ delay3 ] list_of_net_ident_or_decl_assign ';' | 'trireg' [ 'vectored' | 'scalared' ] [ '(' charge_strgth ')' ] [ range ] [ delay3 ] list_of_net_identifiers ';' | 'wreal' list_of_wreal_nets ';'
list_of_wreal_nets ::= IDENTIFIER [ range ] { ',' IDENTIFIER [ range ] }
list_of_net_ident_or_decl_assign ::= IDENTIFIER list_of_net_ident_or_decl_assign_end
list_of_net_ident_or_decl_assign_end ::= '=' expression { ',' net_decl_assignment } | { ',' IDENTIFIER }
net_decl_assignment ::= IDENTIFIER '=' expression
net_type ::= 'wire' | 'tri' | 'tri1' | 'supply0' | 'wand' | 'triand' | 'tri0' | 'supply1' | 'wor' | 'trior'
list_of_net_identifiers ::= IDENTIFIER { ',' IDENTIFIER }
drive_strgth ::= '(' strength_or_high ',' strength_or_high ')'
strength_or_high ::= strength0 | strength1 | high
strength0 ::= 'supply0' | 'strong0' | 'pull0' | 'weak0'
strength1 ::= 'supply1' | 'strong1' | 'pull1' | 'weak1'
high ::= 'highz1' | 'highz0'
charge_strgth ::= 'small' | 'medium' | 'large'
delay3 ::= '#' delay3_end
delay3_end ::= simple_delay_value | '(' del_value [ ',' del_value [ ',' del_value ] ] ')'
delay2 ::= '#' delay2_end
delay2_end ::= simple_delay_value | '(' del_value [ ',' del_value ] ')'
del_value ::= constant_mintypmax_expression
simple_delay_value ::= identifier | number
function_declaration ::= 'function' [ range_or_type ] IDENTIFIER ';' function_item_declaration { function_item_declaration } statement 'endfunction'
range_or_type ::= 'integer' | 'real' | 'realtime' | 'time' | range
function_item_declaration ::= block_item_declaration | input_declaration
task_declaration ::= 'task' IDENTIFIER ';' { task_argument_declaration } [ statement_or_null ] 'endtask'
task_argument_declaration ::= block_item_declaration | output_declaration | input_declaration | inout_declaration
block_item_declaration ::= parameter_declaration | reg_declaration | integer_declaration | real_declaration | time_declaration | realtime_declaration | event_declaration
gate_instantiation ::= n_input_gatetype n_input_gate_instantiation ';' | n_output_gatetype n_output_gate_instantiation ';' | enable_gatetype enable_gate_instantiation ';' | mos_switchtype [ delay3 ] mos_switch_instance { ',' mos_switch_instance } ';' | pass_switchtype pass_switch_instance { ',' pass_switch_instance } ';' | pass_en_switchtype [ delay3 ] pass_en_switch_instance { ',' pass_en_switch_instance } ';' | cmos_switchtype [ delay3 ] cmos_switch_instance { ',' cmos_switch_instance } ';' | 'pullup' pullup_instantiation ';' | 'pulldown' pulldown_instantiation ';'
n_input_gate_instantiation ::= '#' delay2_end n_input_gate_instance { ',' n_input_gate_instance } | '(' n_input_gate_instantiation_2 | name_of_gate_instance '(' output_terminal ',' input_terminal { ',' input_terminal } ')' { ',' n_input_gate_instance }
n_input_gate_instantiation_2 ::= drv_strength_2 [ delay2 ] n_input_gate_instance { ',' n_input_gate_instance } | output_terminal ',' input_terminal { ',' input_terminal } ')' { ',' n_input_gate_instance }
drv_strength_2 ::= strength_or_high ',' strength_or_high ')'
n_output_gate_instantiation ::= '#' delay2_end n_output_gate_instance { ',' n_output_gate_instance } | '(' n_output_gate_instantiation_2 | name_of_gate_instance '(' output_terminal ',' input_or_output_terminal { ',' input_or_output_terminal } ')' { ',' n_output_gate_instance }
n_output_gate_instantiation_2 ::= drv_strength_2 [ delay2 ] n_output_gate_instance { ',' n_output_gate_instance } | output_terminal ',' input_or_output_terminal { ',' input_or_output_terminal } ')' { ',' n_output_gate_instance }
pullup_instantiation ::= name_of_gate_instance '(' output_terminal ')' { ',' pull_gate_instance } | '(' pullup_instantiation_2
pullup_instantiation_2 ::= pullup_strength_2 pull_gate_instance { ',' pull_gate_instance } | output_terminal ')' { ',' pull_gate_instance }
pullup_strength_2 ::= strength0 [ ',' strength1 ] ')' | strength1 [ ',' strength0 ] ')'
pulldown_instantiation ::= name_of_gate_instance '(' output_terminal ')' { ',' pull_gate_instance } | '(' pulldown_instantiation_2
pulldown_instantiation_2 ::= pulldown_strength_2 pull_gate_instance { ',' pull_gate_instance } | output_terminal ')' { ',' pull_gate_instance }
pulldown_strength_2 ::= strength1 [ ',' strength0 ] ')' | strength0 [ ',' strength1 ] ')'
enable_gate_instantiation ::= '#' delay3_end enable_gate_instance { ',' enable_gate_instance } | '(' enable_gate_instantiation_2 | name_of_gate_instance '(' output_terminal ',' input_terminal ',' enable_terminal ')' { ',' enable_gate_instance }
enable_gate_instantiation_2 ::= drv_strength_2 [ delay3 ] enable_gate_instance { ',' enable_gate_instance } | output_terminal ',' input_terminal ',' enable_terminal ')' { ',' enable_gate_instance }
n_input_gate_instance ::= [ name_of_gate_instance ] '(' output_terminal ',' input_terminal { ',' input_terminal } ')'
n_output_gate_instance ::= [ name_of_gate_instance ] '(' output_terminal ',' input_or_output_terminal { ',' input_or_output_terminal } ')'
input_or_output_terminal ::= expression
enable_gate_instance ::= [ name_of_gate_instance ] '(' output_terminal ',' input_terminal ',' enable_terminal ')'
mos_switch_instance ::= [ name_of_gate_instance ] '(' output_terminal ',' input_terminal ',' enable_terminal ')'
pass_switch_instance ::= [ name_of_gate_instance ] '(' inout_terminal ',' inout_terminal ')'
pass_en_switch_instance ::= [ name_of_gate_instance ] '(' inout_terminal ',' inout_terminal ',' enable_terminal ')'
cmos_switch_instance ::= [ name_of_gate_instance ] '(' output_terminal ',' input_terminal ',' ncontrol_terminal ',' pcontrol_terminal ')'
pull_gate_instance ::= [ name_of_gate_instance ] '(' output_terminal ')'
name_of_gate_instance ::= IDENTIFIER [ range ]
pullup_strength ::= '(' pullup_strength_2
pulldown_strength ::= '(' pulldown_strength_2
input_terminal ::= expression
enable_terminal ::= expression
ncontrol_terminal ::= expression
pcontrol_terminal ::= expression
output_terminal ::= identifier [ '[' constant_expression ']' ]
inout_terminal ::= identifier [ '[' constant_expression ']' ]
n_input_gatetype ::= 'and' | 'nand' | 'or' | 'nor' | 'xor' | 'xnor'
n_output_gatetype ::= 'buf' | 'not'
enable_gatetype ::= 'bufif0' | 'bufif1' | 'notif0' | 'notif1'
mos_switchtype ::= 'nmos' | 'pmos' | 'rnmos' | 'rpmos'
pass_switchtype ::= 'tran' | 'rtran'
pass_en_switchtype ::= 'tranif0' | 'tranif1' | 'rtranif0' | 'rtranif1'
cmos_switchtype ::= 'cmos' | 'rcmos'
module_or_udp_instantiation_or_net_discipline_declaration ::= IDENTIFIER module_or_udp_instantiation_or_net_discipline_declaration_2
module_or_udp_instantiation_or_net_discipline_declaration_2 ::= '(' module_or_udp_instantiation_or_net_discipline_declaration_3 | '#' parameter_value_assignment_2 | simple_delay_value [ name_of_instance ] '(' [ module_or_udp_instance_end ] ')' { ',' module_or_udp_instance } ';' | IDENTIFIER [ range ] '(' [ module_or_udp_instance_end ] ')' { ',' module_or_udp_instance } | { ',' IDENTIFIER [ range ] } ';' | range list_of_nets ';'
module_or_udp_instantiation_or_net_discipline_declaration_3 ::= drv_strength_2 [ '#' parameter_value_assignment_2 | simple_delay_value ] module_or_udp_instance { ',' module_or_udp_instance } ';' | [ module_or_udp_instance_end ] ')' { ',' module_or_udp_instance } ';'
module_or_udp_instance ::= [ name_of_instance ] '(' [ module_or_udp_instance_end ] ')'
module_or_udp_instance_end ::= named_port_connection { ',' named_port_connection } | ordered_port_connection { ',' ordered_port_connection }
parameter_value_assignment_2 ::= '(' constant_expression { ',' constant_expression } | named_param_override { ',' named_param_override } ')'
named_param_override ::= '.' IDENTIFIER '(' constant_expression ')'
name_of_instance ::= IDENTIFIER [ range ]
ordered_port_connection ::= [ net_expression ]
named_port_connection ::= '.' IDENTIFIER '(' [ net_expression ] ')'
net_expression ::= identifier [ '[' expression [ ':' constant_expression ] ']' ] | net_concatenation
net_concatenation ::= '{' net_expression { ',' net_expression } '}'
udp_declaration ::= primitive_keyword IDENTIFIER '(' udp_port_list ')' ';' udp_port_declaration { udp_port_declaration } udp_body 'endprimitive'
primitive_keyword ::= 'primitive'
udp_port_list ::= IDENTIFIER ',' IDENTIFIER { ',' IDENTIFIER }
udp_port_declaration ::= output_declaration | input_declaration | reg_declaration
udp_body ::= combinational_or_sequential_body
combinational_or_sequential_body ::= [ udp_initial_statement ] 'table' combinational_or_sequential_entry { combinational_or_sequential_entry } 'endtable'
combinational_or_sequential_entry ::= level_or_edge_input_list ':' level_symbol comb_or_seq_entry_end
comb_or_seq_entry_end ::= ':' next_state ';' | ';'
level_or_edge_input_list ::= { level_symbol } [ edge_indicator { level_symbol } ]
next_state ::= output_symbol | '-'
edge_indicator ::= '(' level_symbol level_symbol ')' | edge_symbol
edge_symbol ::= 'R' | 'F' | 'P' | 'N' | '*'
output_symbol ::= '0' | '1' | 'X'
level_symbol ::= '0' | '1' | 'X' | '?' | 'B'
udp_initial_statement ::= 'initial' identifier '=' init_val ';'
init_val ::= BINARY NUMBER | DECIMAL NUMBER
connectmodule_declaration ::= 'connectmodule' IDENTIFIER '(' connect_port ',' connect_port ')' ';' [ connectmodule_items ] 'endmodule'
connect_port ::= IDENTIFIER
connectmodule_items ::= { connectmodule_item }
connectmodule_item ::= module_item | net_resolution_task
net_resolution_task ::= 'net_resolution' '(' net_or_port_scalar_expression ',' analog_expression ')'
connect_specification ::= 'connectrules' IDENTIFIER ';' { connect_spec_item } 'endconnectrules' ';'
connect_spec_item ::= 'connect' IDENTIFIER connect_insertion | connect_resolution
connect_insertion ::= connect_attributes [ [ direction ] IDENTIFIER ',' [ direction ] IDENTIFIER ] ';'
connect_attributes ::= [ connect_mode ] [ '#' '(' attribute_list ')' ]
connect_mode ::= 'merge[d]' | 'split'
attribute_list ::= connect_attribute { ',' connect_attribute }
connect_attribute ::= '.' IDENTIFIER '(' expression ')'
direction ::= 'input' | 'output' | 'inout'
connect_resolution ::= discipline_list 'resolveto' IDENTIFIER ';'
discipline_list ::= { ',' IDENTIFIER }
analog_block ::= analog_statement
analog_statement ::= analog_seq_block | analog_contribution_or_procedural_assignment | ad_conditional_statement | ad_for_statement | ad_case_statement | event_control_statement | system_task_enble | ad_loop_statement
ad_statement ::= seq_block | procedural_assignment ';' | ad_conditional_statement | ad_for_statement | ad_case_statement | ad_loop_statement
event_control_statement ::= evt_control statement_or_null
ad_expression ::= expression
ad_loop_statement ::= 'while' '(' expression ')' ad_statement | 'repeat' '(' expression ')' ad_statement
analog_seq_block ::= 'begin' [ ':' IDENTIFIER { block_item_declaration } ] { analog_statement } 'end'
analog_statement_or_null ::= analog_statement | ';'
analog_contribution_or_procedural_assignment ::= identifier '=' analog_expression ';' | '[' expression ']' '=' analog_expression ';' | '(' analog_signal_list ')' analog_branch_contribution | analog_indirect_branch_assignment
analog_branch_contribution ::= '<+' analog_expression ';'
analog_indirect_branch_assignment ::= ':' nexpr '==' analog_expression ';'
nexpr ::= access_function_reference | 'ddt' '(' access_function_reference ')' | 'idt' '(' access_function_reference ')'
ad_conditional_statement ::= 'if' '(' ad_expression ')' analog_statement_or_null [ 'else' analog_statement_or_null ]
case_kw ::= 'case' | 'casex' | 'casez'
ad_case_statement ::= case_kw '(' ad_expression ')' ad_case_item { ad_case_item } 'endcase'
ad_case_item ::= ad_expression { ',' ad_expression } ':' analog_statement_or_null | 'default' [ ':' ] analog_statement_or_null
ad_for_statement ::= 'for' '(' procedural_assignment ';' ad_expression ';' procedural_assignment ')' analog_statement
lexpr ::= identifier | [ '[' expression ']' ]
procedural_assignment ::= lexpr '=' expression
global_event ::= 'initial_step' [ '(' analysis_list ')' ] | 'final_step' [ '(' analysis_list ')' ]
analysis_list ::= analysis_name { ',' analysis_name }
analysis_name ::= STRING
event_function ::= cross_function | timer_function | driver_update_function
cross_function ::= 'cross' '(' arg_list ')'
timer_function ::= 'timer' '(' arg_list ')'
driver_update_function ::= 'driver_update' '(' net_or_port_scalar_expression ')'
continuous_assign ::= 'assign' [ drive_strgth ] [ delay3 ] list_of_net_assignments ';'
list_of_net_assignments ::= net_assignment { ',' net_assignment }
net_assignment ::= net_lvalue '=' expression
initial_construct ::= 'initial' statement
always_construct ::= 'always' statement
statement ::= assign_or_task_enable | procedural_continuous_assignment | procedural_timing_control_statement | conditional_statement | case_statement | loop_statement | wait_statement | disable_statement | event_trigger | seq_block | par_block | system_task_enble | repeat_statement_or_event_control
statement_or_null ::= statement | ';'
assign_or_task_enable ::= reg_lvalue assign_or_task_enable_end
assign_or_task_enable_end ::= '=' [ delay_or_event_control ] expression ';' | '<-' [ delay_or_event_control ] expression ';' | [ '(' expression { ',' expression } ')' ] ';'
procedural_continuous_assignment ::= 'assign' reg_assignment ';' | 'deassign' reg_lvalue ';' | 'force' net_or_reg_assignment ';' | 'release' net_or_reg_lvalue ';'
procedural_timing_control_statement ::= delay_control | evt_control statement_or_null
delay_or_event_control ::= delay_control | evt_control | repeat_event_control
repeat_event_control ::= 'repeat' '(' expression ')' evt_control
delay_control ::= '#' delay_control_end
delay_control_end ::= simple_delay_value | '(' mintypmax_expression ')'
evt_control ::= '@' event_control_end
event_control_end ::= identifier | '(' event_expression ')'
event_expression ::= primary_event_expression [ 'or' event_expression ]
primary_event_expression ::= 'posedge' expression | 'negedge' expression | global_event | event_function | expression
conditional_statement ::= 'if' '(' expression ')' statement_or_null [ 'else' statement_or_null ]
case_statement ::= 'case' '(' expression ')' case_item { case_item } 'endcase' | 'casez' '(' expression ')' case_item { case_item } 'endcase' | 'casex' '(' expression ')' case_item { case_item } 'endcase'
case_item ::= expression { ',' expression } ':' statement_or_null | 'default' [ ':' ] statement_or_null
loop_statement ::= 'forever' statement | 'while' '(' expression ')' statement | 'for' '(' reg_assignment ';' expression ';' reg_assignment ')' statement
repeat_statement_or_event_control ::= 'repeat' '(' expression ')' event_control_or_statement
event_control_or_statement ::= statement
reg_assignment ::= reg_lvalue '=' expression
net_or_reg_assignment ::= net_or_reg_lvalue '=' expression
wait_statement ::= 'wait' '(' expression ')' statement_or_null
event_trigger ::= '->' identifier ';'
disable_statement ::= 'disable' identifier ';'
seq_block ::= 'begin' [ ':' identifier { block_item_declaration } ] { statement } 'end'
par_block ::= 'fork' [ ':' identifier { block_item_declaration } ] { statement } 'join'
system_task_enble ::= system_task_name [ '(' [ expression ] { ',' [ expression ] } ')' ] ';'
system_task_name ::= '$' IDENTIFIER
specify_block ::= 'specify' { specify_item } 'endspecify'
specify_item ::= specparam_declaration | path_declaration | system_timing_check
specparam_declaration ::= 'specparam' list_of_specparam_assignments ';'
list_of_specparam_assignments ::= specparam_assignment { ',' specparam_assignment }
specparam_assignment ::= IDENTIFIER '=' constant_mintypmax_expression | pulse_control_specparam
pulse_control_specparam ::= '$PATHPULSE' pulse_control_specparam_end
pulse_control_specparam_end ::= '=' '(' limit_value [ ',' limit_value ] ')' | specify_input_terminal_descriptor '$' specify_output_terminal_descriptor '=' '(' limit_value [ ',' limit_value ] ')'
limit_value ::= constant_mintypmax_expression
path_declaration ::= state_dependent_path_declaration ';' | edge_or_simple_path_declaration ';'
edge_or_simple_path_declaration ::= path_description '=' path_delay_value
path_description ::= '(' [ edge_identifier ] list_of_path_inputs [ polarity_operator ] path_description_end
path_description_end ::= '=>' specify_output_terminal_descriptor | par_edge_sens_path_desc_end ')' | '*>' list_of_path_outputs | full_edge_sens_path_desc_end ')'
par_edge_sens_path_desc_end ::= '(' specify_output_terminal_descriptor [ polarity_operator ] ':' data_source_expression ')'
full_edge_sens_path_desc_end ::= '(' list_of_path_outputs [ polarity_operator ] ':' data_source_expression ')'
list_of_path_inputs ::= specify_input_terminal_descriptor { ',' specify_input_terminal_descriptor }
list_of_path_outputs ::= specify_output_terminal_descriptor { ',' specify_output_terminal_descriptor }
specify_input_terminal_descriptor ::= identifier [ '[' constant_expression [ ':' constant_expression ] ']' ]
specify_output_terminal_descriptor ::= identifier [ '[' constant_expression [ ':' constant_expression ] ']' ]
polarity_operator ::= '+' | '-'
path_delay_value ::= simple_path_delay_expression list_of_path_delay_expressions_end | '(' list_of_path_delay_expressions ')'
list_of_path_delay_expressions ::= path_delay_expression [ ',' path_delay_expression [ ',' path_delay_expression [ ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression [ ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ] ] ] ]
list_of_path_delay_expressions_end ::= [ ',' path_delay_expression [ ',' path_delay_expression [ ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression [ ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ] ] ] ]
path_delay_expression ::= constant_mintypmax_expression
simple_path_delay_expression ::= identifier | number [ ':' constant_expression ':' constant_expression ]
data_source_expression ::= expression
edge_identifier ::= 'posedge' | 'negedge'
state_dependent_path_declaration ::= 'if' '(' expression ')' edge_or_simple_path_declaration | 'ifnone' edge_or_simple_path_declaration
system_timing_check ::= '$' system_timing_check_end
system_timing_check_end ::= 'setup' '(' timing_check_event ',' timing_check_event ',' timing_check_limit [ ',' notify_register ] ')' ';' | 'hold' '(' timing_check_event ',' timing_check_event ',' timing_check_limit [ ',' notify_register ] ')' ';' | 'period' '(' controlled_timing_check_event ',' timing_check_limit [ ',' notify_register ] ')' ';' | 'width' '(' controlled_timing_check_event ',' timing_check_limit [ ',' constant_expression [ ',' notify_register ] ] ')' ';' | 'skew' '(' timing_check_event ',' timing_check_event ',' timing_check_limit [ ',' notify_register ] ')' ';' | 'recovery' '(' controlled_timing_check_event ',' timing_check_event ',' timing_check_limit [ ',' notify_register ] ')' ';' | 'setuphold' '(' timing_check_event ',' timing_check_event ',' timing_check_limit ',' timing_check_limit [ ',' notify_register ] ')' ';' | 'nochange' '(' timing_check_event ',' timing_check_event ',' timing_check_limit ',' timing_check_limit [ ',' notify_register ] ')' ';'
timing_check_event ::= [ timing_check_event_control ] specify_terminal_descriptor [ '&&&' timing_check_condition ]
specify_terminal_descriptor ::= specify_input_terminal_descriptor
controlled_timing_check_event ::= timing_check_event_control specify_terminal_descriptor [ '&&&' timing_check_condition ]
timing_check_event_control ::= 'posedge' | 'negedge' | edge_control_specifier
edge_control_specifier ::= 'edge' '[' edge_descriptor { ',' edge_descriptor } ']'
edge_descriptor ::= '01' | '10' | '0x' | 'x1' | '1x' | 'x0'
timing_check_condition ::= scalar_timing_check_condition
scalar_timing_check_condition ::= expression [ scal_ti_che_cond_end ]
scal_ti_che_cond_end ::= '==' scalar_constant | '===' scalar_constant | '!=' scalar_constant | '!==' scalar_constant
timing_check_limit ::= mintypmax_expression
scalar_constant ::= BINARY NUMBER | DECIMAL NUMBER
notify_register ::= identifier
analog_expression ::= expression
analog_operator_arg_list ::= analog_operator_argument { ',' analog_operator_argument }
analog_operator_argument ::= expression
analog_operator ::= 'ddt' | 'idt' | 'idtmod' | 'absdelay' | 'transition' | 'slew' | 'laplace_zd' | 'laplace_zp' | 'laplace_np' | 'laplace_nd' | 'zi_zp' | 'zi_zd' | 'zi_np' | 'zi_nd' | 'last_crossing' | 'ac_stim' | 'limexp' | 'white_noise' | 'flicker_noise' | 'noise_table'
genvar_expression ::= expression
genvar_assignment ::= identifier '=' genvar_expression
net_lvalue ::= simple_or_multiple_concatenation | identifier [ net_lvalue_end ]
net_lvalue_end ::= '[' expression [ ':' expression ] ']'
reg_lvalue ::= simple_or_multiple_concatenation | identifier [ reg_lvalue_end ]
reg_lvalue_end ::= '[' expression [ ':' expression ] ']'
constant_mintypmax_expression ::= constant_expression [ ':' constant_expression ':' constant_expression ]
mintypmax_expression ::= expression [ ':' expression ':' expression ]
expression ::= logical_or_exp [ '?' expression ':' expression ]
logical_or_exp ::= logical_and_exp { '||' logical_and_exp }
logical_and_exp ::= bit_wise_or_exp { '&&' bit_wise_or_exp }
bit_wise_or_exp ::= bit_wise_excl_or_exp { '|' | '~|' bit_wise_excl_or_exp }
bit_wise_excl_or_exp ::= bit_wise_and_exp { '^' | '~^' | '^~' bit_wise_and_exp }
bit_wise_and_exp ::= equality_expr { '&' | '~&' equality_expr }
equality_expr ::= compare_expr { '==' | '!=' | '===' | '!==' compare_expr }
compare_expr ::= shift_expr { '<' | '<-' | '>' | '>=' shift_expr }
shift_expr ::= add_expr { '<<' | '>>' add_expr }
add_expr ::= factor { '+' | '-' factor }
factor ::= operand { '*' | '/' | '%' operand }
operand ::= [ unary_operator ] primary
unary_operator ::= '+' | '-' | '!' | '~' | '&' | '~&' | '|' | '~|' | '^' | '~^' | '^~'
primary ::= number | ident_or_func_call_or_attr_ref | simple_or_multiple_concatenation | '(' mintypmax_expression ')' | system_function_call | STRING | 'analysis' '(' arg_list ')' | analog_operator '(' analog_operator_arg_list ')' | built_in_function '(' arg_list ')'
ident_or_func_call_or_attr_ref ::= IDENTIFIER [ '.' hierarchical_aux | '(' args ')' | '[' expression [ ':' constant_expression ] ']' ]
hierarchical_aux ::= ident_or_func_call_or_attr_ref | pot_or_flow '.' nature_attribute
args ::= expression { ',' expression } | port_scalar_expression
system_function_call ::= '$' IDENTIFIER | 'time' | 'realtime' [ '(' [ expression ] { ',' [ expression ] } ')' ]
number ::= DECIMAL NUMBER | OCTAL NUMBER | BINARY NUMBER | HEXADECIMAL NUMBER | REAL NUMBER
simple_or_multiple_concatenation ::= '{' expression [ som_concatenation_end ] '}'
som_concatenation_end ::= ',' expression { ',' expression } | '{' expression { ',' expression } '}'
constant_expression ::= constant_logical_or_exp [ '?' constant_expression ':' constant_expression ]
constant_logical_or_exp ::= constant_logical_and_exp { '||' constant_logical_and_exp }
constant_logical_and_exp ::= constant_bit_wise_or_exp { '&&' constant_bit_wise_or_exp }
constant_bit_wise_or_exp ::= constant_bit_wise_excl_or_exp { '|' | '~|' constant_bit_wise_excl_or_exp }
constant_bit_wise_excl_or_exp ::= constant_bit_wise_and_exp { '^' | '~^' | '^~' constant_bit_wise_and_exp }
constant_bit_wise_and_exp ::= constant_equality_expr { '&' | '~&' constant_equality_expr }
constant_equality_expr ::= constant_compare_expr { '==' | '!=' | '===' | '!==' constant_compare_expr }
constant_compare_expr ::= constant_shift_expr { '<' | '<-' | '>' | '>=' constant_shift_expr }
constant_shift_expr ::= constant_add_expr { '<<' | '>>' constant_add_expr }
constant_add_expr ::= constant_factor { '+' | '-' constant_factor }
constant_factor ::= constant_operand { '*' | '/' | '%' constant_operand }
constant_operand ::= [ unary_operator ] constant_primary | built_in_function '(' const_arg_list ')'
hierarchical_name ::= IDENTIFIER [ '.' identifier [ '.' pot_or_flow '.' nature_attribute ] | pot_or_flow '.' nature_attribute ]
constant_primary ::= number | 'inf' | hierarchical_name | constant_som_concatenation | STRING | constant_mintypmax_expression_or_value_range_specifier
constant_mintypmax_expression_or_value_range_specifier ::= start_paren constant_expression ')' | ':' constant_expression end_paren | ':' constant_expression ')'
constant_som_concatenation ::= '{' constant_expression [ constant_som_concatenation_end ] '}'
constant_som_concatenation_end ::= ',' constant_expression { ',' constant_expression } | '{' constant_expression { ',' constant_expression } '}'
net_or_reg_lvalue ::= simple_or_multiple_concatenation | identifier [ net_or_reg_lvalue_end ]
net_or_reg_lvalue_end ::= '[' expression [ ':' expression ] ']'
identifier ::= IDENTIFIER { '.' IDENTIFIER }
const_arg_list ::= constant_expression { ',' constant_expression }
arg_list ::= expression { ',' expression }
access_function_reference ::= IDENTIFIER '(' analog_signal_list | port_scalar_expression ')'
bvalue ::= IDENTIFIER '(' analog_signal_list ')'
analog_signal_list ::= net_or_port_scalar_expression [ ',' net_or_port_scalar_expression ]
net_or_port_scalar_expression ::= identifier [ '[' genvar_expression ']' ]
pvalue ::= IDENTIFIER '(' port_scalar_expression ')'
port_scalar_expression ::= '<' net_or_port_scalar_expression '>'
built_in_function ::= 'ln' | 'log' | 'exp' | 'sqrt' | 'min' | 'max' | 'abs' | 'pow' | 'ceil' | 'floor' | 'sin' | 'cos' | 'tan' | 'asin' | 'acos' | 'atan' | 'atan2' | 'sinh' | 'cosh' | 'tanh' | 'asinh' | 'acosh' | 'atanh' | 'hypot'