Discipline compatibility for disciplines derived from the same base discipline depends on their attribute compatibility. If attributes differ (e.g. abstol) then there should be a resolution function that takes all the values present and returns the working value, otherwise the disciplines should be considered incompatible.
Attribute resolution functions probably need new syntax e.g.:
discipline electrical resolve abstol = abs_min; // probably in the standard include
or
discipline electrical resolve my_attr = my_func; // my_func is bound later
or
discipline electrical resolve my_attr function begin
//implicit integer my_attr_size
integer n = my_attr_size;
real tot = 0;
while (n-- > 0) tot += my_attr[n];
resolve = avg/my_attr_size; // return average
endfunction
If you have two electrical disciplines with different vdd/vss attributes and without a resolution function for them they would be considered incompatible, and the Verilog-AMS compiler will look for a discipline connection rule (which might be a level shifter module).