- + Issue 16: Mixed signal initialization (digital)

[Kevin Cameron, 01 Dec 2000]


Existing Verilog-D simulators are entirely transient in operation, and therefore don't have any mechanisms for static/steady state simulation. Clearing all the time-zero events won't necessarily help stabilize feedback loops through analog behavior.

For gate-level combinational logic it is possible to evaluate valid steady-state values and therefore close loops, but synchronous logic and behavior usually requires a clock cycle or reset pulse to bring it to a sensible state.

Proposal

We should add a block type to Verilog-D for evaluating module steady-state behavior. We need a syntax which allows multiple event driven processes e.g.: 

module stt_mc(clk,a,b,c,d,q1,q2);

  ....

  steady begin
    
     @(a,b,c,d) begin

       {q1,q2} = chk_func(q1,q2,a,b,c,d); // only allow valid states

     end;

  endsteady;
"steady" blocks would use any Verilog statements that don't involve delays (or delays would be ignored). Data values from the steady-state analysis could/would be discarded after operating point analysis and 'X' values used instead.

N.B. This kind of functionality may be required for arbitrary operating point analysis.