- + Issue 908: (5) Section 3.5 and 7.7.3 - Real value port examples have errors:

[Jon Sanders, 1/22/2001]

  (5) Section 3.5 and 7.7.3 - Real value port examples have errors:
  
    
   The examples in 3.5 and 7.3.3 have errors that prevent them from working without additional changes. The example in 3.5 should
   be changed as follows:
     // The following three lines should be added so that a wreal is passed into foo
     wreal wstim;
     assign wstim=stim;
     foo f1(wstim,load);
     // foo f1(stim,load); //This line should be deleted3 as it is illegal for ports of type real
     // dut d1 (load, out); // This line should be deleted as it provides not added value
   The example in 7.3.3 should be changed as follows:
   First there is no top level module that instantiates the two blocks so add:
     module top ();
      
     wreal stim;
     reg clk;
     wire [1:8] out;
     teststim tb1 (stim, clk);
     a2d dut (out, stim, clk);
     initial clk=0;
     always #1 clk=~clk;
     endmodule
    
   In addition, the testbench module must be converted to use wreal since it is passing a real value through one of its ports
   (the whole reason for wreal). The following fixes this issue:
     module teststim (wout,clk); // change output port to wout
     input clk;
     output wout; // change output port from out to wout
     real out;
     wire clk;
     wreal wout; // add wout declaration as type wreal
     assign wout=out; // assign wreal (wout) value to be value of real (out)
     ....
     Recommendations: Make the above changes as shown