Discipline name logic in disciplines.vams conflicts with keyword in SystemVerilog for a variable type logic.
[Comment]
This problem is excerbated by the way Verilog is parsed: all input is consider as a single data stream, so there is no "file" scope. A general solution would be to use typedefs for logic etc. and to add a mechanism for forgetting a typedef (like `define/`undef in the preprocessor) e.g.:
// SV source typedef _sv_logic logic; // maybe implied .... untypedef logic; `include "old.v" typedef _sv_logic logic; // restore meaning