// Integrator model with limitations on the output

module top;
 wire in, out;

 V_limited_integrator i1(in,out);
endmodule

module V_limited_integrator(in,out);
 input in;
 output out;
 voltage vin,vout;
 parameter real ki=1.0 exclude 0,       // integration coefficient
                lower_limit=-1.0,       // lower limit for output value
                upper_limit= 1.0 from (lower_limit:inf),
                                        // upper limit for output value
                dcval = 0.0;            // initial condition

 real ic;
 integer mode;
 real k1;

 initial k1 = 1/ki;

`define bottom -1
`define active 0
`define top 1

 analog
   begin
    if (mode != `active)
    begin                               // check mode of integrator
      if ((mode == `top) && (V(in) < 0))
        mode = `active;
      else if ((mode == `bottom) && (V(in) > 0))
        mode = `active;
    end
    else
    begin
      if (V(out) >= upper_limit)
      begin
        mode = `top;
        ic = upper_limit;
      end
      else if (V(out) <= lower_limit)
      begin
        mode = `bottom;
        ic = lower_limit;
      end
    end
    if (analysis("static"))
      V(out) <+ idt(V(in), dcval);
    else
      V(out) <+ k1 * idt(V(in), ic, mode);
  end
endmodule