// symmetric clock generator

module clock_generator(clk);
 output clk;
 voltage clk;

 parameter real clk_period = 10n from (0:inf),
                clk_ratio = 0.5 from (0:1),
                clk_high = 5.0,
                clk_low  = 0.0 from (-inf:clk_high),
                trise = 1n from [0:inf),
                tfall = 1n from [0:inf);

 analog
 begin
   if (analysis("static"))
     V(clk) <+ clk_low;
   else
     @(timer(0,clk_period))
     begin
        V(clk) <+ transition(clk_high,
                             clk_period*clk_ratio - trise/2,trise);
        V(clk) <+ transition(clk_low,
                             clk_period - tfall/2,trise,tfall);
     end
 end
endmodule