module firstorder_sigmadelta(in,clk,out);
 input in,clk;
 output out;
 voltage in,clk,out;
 parameter real quantizer_vth=0.0;
 parameter real clk_vth=2.5;
 parameter real d2a_gain=5.0;

 real vsum;
 real vd;
 real vint;
 real vout;
 real hi,lo;

 analog
 begin
   @(initial_step)
   begin
     vd=0;vint=0;vout=0;
     hi = 1; lo = -1;
   end

   @(cross(V(clk) - clk_vth,1))
   begin
// summing junction
     vsum = V(in) - vd ;
// integrator
     vint = vint + vsum;
// quantizer
     if (vint > quantizer_vth) vout = hi ;
     else                      vout = lo ;
// D to A
     vd = d2a_gain*vout ;
   end
   V(out) <+ vout ;
 end
endmodule