module V_not(in,out);
 input [0:size-1] in;
 output [0:size-1] out;
 electrical in,out;

 parameter real size = 1 from [1:inf),
                vout_high = 5,
                vout_low = 0 from (-inf:vout_high),
                vth = 1.4,
                tdelay = 5n from [0:inf),
                trise = 1n from [0:inf),
                tfall = 1n from [0:inf);

 analog
   generate i (0,size-1)
   begin
     @(cross(V(in[i]) - vth, +1))
       V(out) <+ transition(vout_high,tdelay,trise,tfall);
     @(cross(V(in[i]) - vth, -1))
       V(out) <+ transition(vout_low ,tdelay,trise,tfall);
   end
endmodule