module V_or(in,out);
 input [0:size-1] in;
 output out;
 voltage in,out;

 parameter real size = 2 from [2:inf),
                vout_high = 5,
                vout_low = 0 from (-inf:vout_high),
                vth = 1.4,
                tdelay = 5n from [0:inf),
                trise = 1n from [0:inf),
                tfall = 1n from [0:inf);

 integer instate[0:size-1];
 integer out_state;
 real vout;

 analog
 begin
   @(initial_step)
     for(i=0;i<size;i=i+1) in_state=0;

   generate i (0,size-1)
   begin
     @(cross(V(in[i]) - vth))
     begin
       in_state[i] = V(in[i]) > vth;
       out_state = 0;
       for (i=0;i<size;i=i+1)
         if (in_state[i]) out_state = 1;
       if (out_state) vout = vout_high;
       else           vout = vout_low;
     end
   end

   V(out) <+ transition(vout,tdelay,trise,tfall);
 end
endmodule