// sampler:
//      Hierarchical connection of the clock generator and sample_hold model
//      to describe a sample&hold circuit.
//

module sampler(in,out)
 input in;
 output out
 voltage in,out;

 parameter real clk_period = 5n from (0:inf);
 parameter real slewrate = 1.0n from (0:inf);
 parameter real clk_high = 5.0;
 parameter real clk_low  = 0.0 from (-inf:clk_high);


 clock_generator  #(clk_period,clk_high,clk_low)
                        clock(clk);
 sample_hold       #(slewrate,(clk_high-clk_low)/2)
                        S_H(in,out,clk);
endmodule