Re: $mfactor in Verilog-style netlists

Kevin Cameron wrote:
>
> You could tweak the syntax to be either a range or a multiplier, and you could add extra functionality/syntax to the module declaration to indicate that it will handle multipiers internally when possible (rather than actually having multiple instances).

It would be nicer to have the multiplier, [constant_expression],
rather than a range such that [expr1:expr2] means you have
(expr2 - expr1 + 1) instances in parallel.

As to the second half of your statement: we DO NOT want the module
to have to have anything special set up inside, the model writer
should be oblivious to this (unless he/she is doing something
special).

> The advantage of the integer range is that it is compatible with both analog and digital module instantiation, so the parent module doesn't need to differentiate - and it's backward compatible.

Hmm ...

> > 3. Some voltage sources (like inductors) will not converge in DC in many simulators
> > due to a voltage source loop.
> >
> How is that related?

If you set m=3 for an inductor, you don't want to put three in
parallel, because they are shorts at dc, so you can't solve the
dc operating point (you can have an arbitrary loop current
through any two).

However, if you look at the Verilog-A contribution statement:

  V(a,b) <+ ddt( L * I(a,b));

then our rules say: I(a,b) is divided by m. (This is equivalent
to saying the effective inductance is L/m.) You no longer have
the loop problem. The simulator should be able to figure this
out automatically, without requiring "multiplier" to be
declared in the module.

-Geoffrey
Received on Wed Apr 7 13:23:16 2004