RE: Paramset Proposal

From: Kevin Cameron <k.cameron@cputech.com>
Date: Thu May 13 2004 - 16:10:06 PDT

 

I just had a look at the paramset proposal on the website,

and I'm a bit concerned about the mechanism for selecting

between multiple sets of the same name: the proposal appears

rule-based but doesn't seem to have any rules for when multiple

matches are valid.

 

I think some procedural decision making probably needs to be

added to prioritize paramset selection. Since parameters are

processed in the same phase of elaboration as generate statements

I think you could view a paramset as similar to a chunk of code to

be processed in the manner of a generate statement when a module

is instantiated (after local parameters have been processed).

E.g.:

 

  module ntran1 (g,s,d)

      parameter l,w;

      ...

  endmodule

  

  module ntran2 (g,s,d)

      parameter l,w;

      parameter real as=50f;

      ...

  endmodule

  

  paramset ntran (ntran1,ntran2 /* applicable modules */)

    // model parameters

    parameter real tox = ...;

    ...

    // instance parameters

    if ($param_given(l) && $param_given(w)) begin

      parameter real area = l * w;

      if (l > w) paramset ntran_long; // include geometry specific
parameters

      else paramset ntran_short;

      if (!$param_given(as)) parameter as = GuessAS(l,w); // fix ntran1

    end

    assert(area > `AREA_MIN); // bad instance ?

  endparamset

 

 

You could view the paramset as being like a function that returns a

list of parameters.

 

This might be faster to process and easier to debug than the rule-based

approach, but it doesn't exclude using it as well.

 

Kev.

 

Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862

 

 

> -----Original Message-----

> From: owner-verilog-ams-devmod@eda.org
[mailto:owner-verilog-ams-devmod@eda.org] On Behalf Of

> Geoffrey.Coram

> Sent: Thursday, May 13, 2004 1:51 PM

> To: VerilogA Device Modeling Reflector

> Subject: new proposal doc

>

> As hoped, I have now placed a revised version of the

> device modeling proposal on the web site.

>

> http://www.eda.org/verilog-ams/htmlpages/compact.html

>

> It includes section numbers for the LRM.

>

> -Geoffrey
Received on Thu May 13 16:10:11 2004

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