Re: descriptions

Geoffrey,

I think we should be consistent across the language. So if we are going
with the " ---"description string" " format then we should define the
rules for it and use it everywhere. You've defined the syntax, the
supported objects this can modified, location in the syntax, sharing with
multiple identifiers, and rules on over defining based on what I see below
in an informal (albeit inconsistent (before and after object) way. Unless
Verilog 2001 or SystemVerilog have better proposals it sounds like a
general extension to the core language, just like attributes were.

Martin, do you want to check with our digital parser guys to see if they
see any problems from a parser perspective?

While " ---"string" " seems pretty easy to parse (except for the dreaded 3
character look ahead) one problem which is the problem we are having with
attributes is the free floating nature of this object. Not sure how you
put this in the BNF that essentially between any objects you can place this
object. Obviously if they modified attributes to be free floating we
could use them but if not then this is the option but it has the same BNF
problem. Since you put the description before some objects and after
others the BNF certainly has to be defined in some way or we need to be
very restrictive.

Jon

At 07:05 AM 5/26/2004, Geoffrey.Coram wrote:
>In the conference call on Monday night, the main AMS
>committee (specifically Martin O'Leary) decided that
>using an attribute for descriptions did not actually
>help compatibility with V-2001, since I insisted that
>the attribute for params, variables, and nets (ports)
>be after the item.
>
>Putting the attribute before the item, to comply with
>V-2001's use of attributes, is ugly:
> (*desc="Forward Early voltage"*) parameter real vef = 44.0 from
> (0.01:inf);
> (*desc="Fraction of the emitter-base depletion capacitance that belongs
> to the sidewall"*) parameter real XCJE = 0.4 from [0.0:1.0];
>
>compared with
> parameter real VEF = 44.0 from (0.01:inf) --- "Forward Early voltage";
> parameter real XCJE = 0.4 from [0.0:1.0] --- "Fraction of the
> emitter-base depletion capacitance that belongs to the sidewall";
>
>
>I see three remaining issues:
>
>1) Module descriptions: it seems to me that we could use
>the attribute for this; having it on the line above the
>module declaration makes it function as a nice comment
>in the code:
> (*desc="Mextram 504 Bipolar transistor model"*)
> module bjt504(c,b,e,s);
>
>
>2) Since V-2001 doesn't have disciplines, putting the port
>description on the discipline declaration line means that
>you can't describe a digital port.
>
>On the other hand, if you put the description on the
>input/output/inout declaration, then you can't describe
>the internal nodes of semiconductor devices.
>
>Presumably, we don't want two ways to attach a description.
>
>
>3) For net/port descriptions, we had allowed a description
>to apply to multiple net_identifiers:
> electrical (*desc="input"*) in1, in2, (*desc="output"*) out;
>
>I don't think this is possible with the --- syntax; do we care?
>You'd have to do
> electrical in1 --- "input", in2 --- "input", out --- "output";
>
>which is still an improvement over V-2001, which would have to do:
> (*desc="input"*) input in1, in2;
> (*desc="output"*) output out;
>
>
>-Geoffrey

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Jonathan L. Sanders
Product Engineering Director
Custom IC Solutions
Cadence Design Systems, Inc.
555 River Oaks Pkwy
San Jose, CA. 95134
  INTERNET:jons@cadence.com Tel: (408) 428-5654 Fax : (408) 944-7027
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Received on Wed May 26 09:27:14 2004